Report

Teaser, summary, work performed and final results

Periodic Reporting for period 1 - TMGSiP (THz Muti-Gb/s System in Package)

Teaser

\"The goal of \"\"THz Muti-Gb/s System in Package\"\", i.e., \"\"TMGSiP\"\" project is to develop a fully integrated 120GHz radio front-end for Multi-Gb/s radio links with state-of-the-art SiGe BiCMOS technology. This will be done with a completely new cross-cutting design methodology...

Summary

\"The goal of \"\"THz Muti-Gb/s System in Package\"\", i.e., \"\"TMGSiP\"\" project is to develop a fully integrated 120GHz radio front-end for Multi-Gb/s radio links with state-of-the-art SiGe BiCMOS technology. This will be done with a completely new cross-cutting design methodology for silicon-MMIC, e.g. the development of wideband receiver and transmitter, including on-chip antenna and novel packaging concepts. This will enable a big improvement in the functionality (complexity of RF MMICs), performance (data rate), component size (fully-integrated compact MMIC with integrated antennas), power consumption and cost over existing III/V communication systems.
The project’s ambition is to realize a sub-THz Si analog front-end with integrated antennas for a line of sight communication link with data rates even up to 40Gbps centered around 120GHz bandwidth of 20GHz and range up to a few meters. Due to the huge available bandwidth only simple low-order modulation schemes like QPSK will be considered. Due to the termination of the project only first building blocks of the wideband transmitter and receiver were designed, fabricated and characterized. Also some preliminary design work of the other building components has been carried out.
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Work performed

The goal of the project is to design a radio front-end operating at 120GHz frequency band. The MMIC will be realized in a standard SiGe Bi-CMOS technology provided by a European factory IHP (www.ihp-microelectronics.com). IHP offers technology node named SG13S which is a high-performance 0.13 µm BiCMOS technology with npn-HBTs up to fT / fmax= 250/340 GHz. The devices offered in this technology have appropriate performance to be used in the designs for the project.
The project begun with the design of the most crucial components of the receiver and the transmitter which are the Low Noise Amplifier (LNA) and the Power Amplifier (PA). The broadband operation with on-chip antenna and proposed novel packaging concept required a dedicated design approach.
In order to enable proposed packaging the active and passive structures of the LNA and PA have to be shielded by a ground plane. To make it possible a dedicated strip-line has been developed and used in the first brake-outs of the transmitter and receiver. All the parameters of the strip-line (width, spacing) have been optimized in electromagnetic (EM) simulations to achieve best possible performance of the circuits.
The first circuit which was designed is the LNA. It comprises a three-stage cascode structure as shown in Figure 1. The circuit was optimized to achieve highest possible bandwidth and gain while minimizing the noise figure. The input and output matching have optimize to achieve match to 50 Ohm in the whole operation bandwidth. The goal of the project was to achieve 20GHz of bandwidth around 120GHz frequency of operation. The careful design and circuit optimization led to achievement of 30GHz of bandwidth centred around 125GHz. The middle of the bandwidth was shifted towards higher frequencies on purpose, since according to my experience the fabricated circuits tend to operate at lower frequencies than simulated due to some extra parasitic components.
The simulated performance of the designed LNA is summarized in Table 1. The LNA achieves 17dB of peak gain and 30GHz of 3dB bandwidth. The simulated noise figure of the LNA exhibits minimum of 9.6dB at 122GHz. The circuits draws 19.6mA from a 3V supply. The simulated S-parameters, NF and linearity are plotted in Figure 2 (a-e) respectively.
As the circuit design of the LNA was ready, the physical layout of the device was designed. It should be noted that the layout design and circuit design are complementary process since all the passive structures and interconnects between components have to be simulated in EM simulator. The design of a circuit operating at 120GHz is an iterative process which involves circuit simulations, careful layout design and layout modelling (using EM simulator). The final design of the LNA layout is depicted in Figure 3. The layout occupies the silicon area of 375um x 700um and it includes all necessary pads for future measurements. The size and distances between the pads are chosen in the way to guarantee that the MMIC can be measured in a HF test laboratory. The layout was also fully verified using Design Rule Check (DRC) and Layout Versus Schematic (LVS) procedures to guarantee manufacturability and topological match between simulation schematic and physical implementation.
The next component designed in the first stage of the project was the power amplifier. The circuit diagram of the implemented amplifier is depicted in Figure 4. It is realized as a three stage cascode with transmission lines as load and inter-stage matching components. The amplifier was optimized to achieve desired bandwidth and maximum output power.
The designed amplifier exhibits a peak gain of 16dB and a bandwidth of 30GHz. The output power at 1dB CP reaches 3.5dBm. The circuit drives 35.5mA from 3V supply resulting in 106.5mW power dissipation.
The simulated S-parameters, linearity and transient output signals signals are plotted in Figure 2 (a-e) respectively.
The physical layout of the PA was realized in simila

Final results

The two designed and fabricated test ICs showed the feasibility of the project. They confirmed that with novel design approach it is possible to realize a RF front-end circuits enabling multi-Gb/s wireless communication in silicon process technologies. Unfortunately, due to the termination of the project the further research on the topic was not continued.