ESL_STR

Automatic Hardware Generation Using the Stream Programming Paradigm

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 Obiettivo del progetto (Objective)

'Electronic System Level (ESL) design is an emerging semiconductor design and verification methodology that focuses on higher levels of abstraction to describe the functionality of a platform system. Elevating the abstraction level closer to the application and away from the implementation details is becoming a vital step for rapid prototyping and productization of complex System on Chips (SoCs). The main promise of the ESL methodology is to enable the developers to focus on the important aspects of their application, and to open up platform design to software and algorithm developers that do not necessarily have hardware and architectural expertise. Unfortunately, the ESL vision remains unfulfilled mainly due to the lack of an acceptable abstraction layer among the researchers and the potential users of ESL tools. The lack of such a common language creates a lack of understanding between designers at different levels, unnecessary replication of tasks, potential for erroneous system functionality, and market fragmentation. We believe that a successful ESL abstraction should provide semantics to express “spatial computation” and should share a lot of common elements with parallel programming for multi-core or many-core engines. In this work, we introduce the stream programming paradigm as an ESL abstraction, and we propose the design and implementation of an ESL tool that generates synthesizable hardware based on this paradigm. The streaming programming paradigm is an emerging embedded domain in which an application can be viewed as a collection of independent kernel computations that communicate over explicit data channels.'

Introduzione (Teaser)

Software developers often have limited expertise in the area of hardware and system architecture design. A novel tool is bridging the gap between desired functionality and hardware implementation.

Descrizione progetto (Article)

Electronic system-level (ESL) design is an innovative semiconductor development and verification methodology that has great potential to aid software developers with automatic design of hardware modules from the high-level representation of a task. However, the language tools required to communicate among the various layers of abstraction are largely lacking resulting in increased time to market.

Scientists sought to exploit stream and data parallelism processing paradigms enabling an application to be seen as multiple individual computational units (kernels) without explicitly managing communication among those units. EU funding of the project 'Automatic hardware generation using the stream programming paradigm' (ESL_STR) enabled them to achieve their goal. The case study was application to a field programmable gate array (FPGA), a semiconductor device that can be 'programmed' by the user (in the field) after manufacturing, rewiring the integrated circuit on the chip itself to produce the desired functionality.

Researchers produced a computer-aided design (CAD) tool to generate the co-processor design for an FPGA. The tool employs Open Computing Language (OpenCL), an industry standard programming environment to write programmes for heterogeneous computing architectures (those with more than one processor) consisting of the host or central processor unit (CPU) and the device or graphics processing unit (GPU). ESL_STR's version, called silicon OpenCL or SOpenCL, maps the parallelism (multiple processors) of an application onto a reconfigurable FPGA. A high-level compiler (HLC) partitions an OpenCL application's kernels across the CPU, GPU and the FPGA itself. A low-level compiler (LLC) processes the kernels selected to run on the FPGA platforms, generating an equivalent hardware design that fulfils performance requirements.

The ESL_STR tool opens the door to code portability across different multi-processor platforms, including both fixed and reconfigurable architectures. Such capability promises to make novel technologies such as FPGAs major players in the high-performance computing game.