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Report

Teaser, summary, work performed and final results

Periodic Reporting for period 1 - Wave-Locked Loop (Wave-Locked Loop for Frequency Synthesis (WLL))

Teaser

Summary

Today, wireless communication has changed the way people lived and turn a mobile device into a necessary equipment in daily life. This has driven the cellular phone industry to support Bluetooth wireless personal area networking and 4G communication where low-cost prototype with low power for RF transceivers, as well as processors are integrated in a low-cost and low-power form factor .This project aims to break this tradeoff in conventional PLLs that constraints the amount of noise rejected by the loop as well as the achievable lock time, while maintaining long battery life time at low cost. Instead of detecting only the phase information for a subsequent correction in each reference cycle [see Fig. 2 (c)], waveform information is captured which is composed of amplitude, phase, and frequency information; hence the term wave-locked loop (WLL). The WLL would be able to provide precise frequency with much faster locking when compared to conventional PLLs. To achieve optimum performance, oscillator phase noise is one of the most important design parameters (out-of-band region). Moreover, design of low-flicker-noise LC DCO and small-sized ring oscillator with phase noise filtering will be investigated. Thus, the research objective of this fellowship program is to produce an innovative frequency synthesizer and clock generation systems using wave-locked loop, which includes the study of oversampling of oscillator waveform for fine phase detection, the study of phase-noise reduction in ring oscillator using discrete-time filtering, the study of mm-wave oscillator with flicker noise corner reduction, and system integration for wave-locked loop system.

Work performed

1. The study of low-power high-resolution digital-to-time converters (DTC) has been studied and verified with chip measurement. We can achieve less than 100fs resolution with 9-bit resolution while consuming less than 100uW of power consumption. Therefore, it is suitable for low-power high-performance ADPLL.
2. To support the upcoming 5G standard, mm-wave Class-F LC-based DCO with low flicker noise corner will be studied has been studied and verified with chip measurement. Class-F oscillator shows competitive performance compared with other oscillator classes but it is much more robust to power supply noise. Since flicker noise corner is usually high in mm-wave oscillators which could be the main noise contributor, we have investigated flicker-noise corner reduction at mm-wave in which the consideration of common-mode inductance and capacitance in the transformer and switched capacitor are carefully modelled and simulated to achieve high common-mode impedance at second harmonic. This results in a flicker noise corner of 130kHz while maintain phase noise figure-of-merit on-par with the state-of-the-art.
3. The study of low-supply ADPLL has been investigated. While digitally-controlled oscillator (DCO) and digital power amplifier (DPA) can directly operate at low supply, time-to-digital converter (TDC) and all digital blocks need higher supply voltage to operate. In particular, if TDC is operated at relatively low supply, its resolution degrades and results in a degradation of in-band phase noise of an ADPLL. Moreover, traditional approach requires additional digital gain calibration to maintain ADPLL performance across process-temperature-voltage (PVT) variations.
4. For energy-efficient 30GHz harmonic extractor, we proposed injection-locked third-harmonic extractor technique which reduce power consumption when compared with traditional approach while maintain output power level at acceptable performance.
5. The study of the oversampled oscillator waveform for precise phase/frequency and amplitude detections and system integration will be studied over a variation of several nonlinearities factor (WP1), i.e., harmonically distorted (both intentional and unintentional) input waveform, nonlinear delays in oversampling clocks, and resolution of ADC. Our study shows finer than 1 ps resolution even with 10% delay error in sampling clocks, and distortion from input waveform. Thus, this approach is suitable for phase detection in all-digital phase-looked loop and it is much more roust and offer much larger dynamic range compared with traditional sub-sampling phase detector.

Final results

The project advances the development of the RF integrated circuit design and techniques for high-frequency and high-performance frequency synthesisers for next-generation communication system such as 5G and automotive radars. Below show detailed of key advancements as a result of this project. The study of low-power high-resolution digital-to-time converters (DTC) has been studied and verified with chip measurement. This research outcome will help reduce power consumption of wireless communication such as Bluetooth Low-Energy (BLE). Therefore, this will help ensure that communication chips will not drain too much of power from mobile phones. Such technique will help break trade-offs in power consumption and achievable jitter performance of all-digital phase-locked loop (ADPLL) which will excel the performance in PLL figure-of-merit (FOM). To support the upcoming 5G standard, mm-wave Class-F LC-based DCO with low flicker noise corner will be studied has been studied and verified with chip measurement. Class-F oscillator shows competitive performance compared with other oscillator classes but it is much more robust to power supply noise. Since flicker noise corner is usually high in mm-wave oscillators which could be the main noise contributor, we have investigated flicker-noise corner reduction at mm-wave in which the consideration of common-mode inductance and capacitance in the transformer and switched capacitor are carefully modelled and simulated to achieve high common-mode impedance at second harmonic. This results in a flicker noise corner of 130kHz while maintain phase noise figure-of-merit on-par with the state-of-the-art. The study of low-supply ADPLL has been investigated. While digitally-controlled oscillator (DCO) and digital power amplifier (DPA) can directly operate at low supply, time-to-digital converter (TDC) and all digital blocks need higher supply voltage to operate. In particular, if TDC is operated at relatively low supply, its resolution degrades and results in a degradation of in-band phase noise of an ADPLL. Moreover, traditional approach requires additional digital gain calibration to maintain ADPLL performance across process-temperature-voltage (PVT) variations. With the help of digital signal processing, phase error in digital domain is detected and by means of negative feedback, supplies of TDC are regulated through the switched-cap voltage doubler. Internal clocks keep adding charge on the supply of the TDC until the value results in the lowest detected phase error. Therefore, this helps maintain a fixed resolution of the TDC over PVT variations and maintain performance across whole range of operation. The study of the oversampled oscillator waveform for precise phase/frequency and amplitude detections and system integration has shown ability to extract fine phase information and possibility to achieve high accuracy in frequency detection in which conventional method cannot be detected.