Mont-Blanc
Mont-Blanc, European scalable and power efficient HPC platform based on low-power embedded technology
| Coordinatore | BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION
Organization address
address: Calle Jordi Girona 31 contact info |
| Nazionalità Coordinatore | Spain [ES] |
| Totale costo | 14˙269˙737 € |
| EC contributo | 8˙110˙000 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2011-7 |
| Funding Scheme | CP |
| Anno di inizio | 2011 |
| Periodo (anno-mese-giorno) | 2011-10-01 - 2015-03-31 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION
Organization address
address: Calle Jordi Girona 31 contact info |
ES (BARCELONA) | coordinator | 0.00 |
| 2 |
ARM LIMITED
Organization address
address: 110 FULBOURN ROAD contact info |
UK (CAMBRIDGE) | participant | 0.00 |
| 3 |
BAYERISCHE AKADEMIE DER WISSENSCHAFTEN
Organization address
address: ALFONS-GOPPEL-STRASSE 11 contact info |
DE (MUENCHEN) | participant | 0.00 |
| 4 |
Bull SAS
Organization address
address: RUE JEAN JAURES 68 contact info |
FR (LES CLAYES SOUS BOIS) | participant | 0.00 |
| 5 |
CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
Organization address
address: Rue Michel -Ange 3 contact info |
FR (PARIS) | participant | 0.00 |
| 6 |
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Organization address
address: RUE LEBLANC 25 contact info |
FR (PARIS 15) | participant | 0.00 |
| 7 |
CONSORZIO INTERUNIVERSITARIO CINECA
Organization address
address: VIA MAGNANELLI 6/3 contact info |
IT (CASALECCHIO DI RENO BO) | participant | 0.00 |
| 8 |
FORSCHUNGSZENTRUM JUELICH GMBH
Organization address
address: WILHELM JOHNEN STRASSE contact info |
DE (JULICH) | participant | 0.00 |
| 9 |
GRAND EQUIPEMENT NATIONAL DE CALCUL INTENSIF
Organization address
address: RUE DE L'EGLISE 12-14 contact info |
FR (PARIS) | participant | 0.00 |
| 10 |
UNIVERSIDAD DE CANTABRIA
Organization address
address: AVENIDA DE LOS CASTROS S/N contact info |
ES (SANTANDER) | participant | 0.00 |
| 11 |
UNIVERSITE JOSEPH FOURIER GRENOBLE 1
Organization address
address: Avenue Centrale, Domaine Universitaire 621 contact info |
FR (GRENOBLE) | participant | 0.00 |
| 12 |
UNIVERSITE MONTPELLIER 2 SCIENCES ET TECHNIQUES
Organization address
address: PLACE EUGENE BATAILLON 2 contact info |
FR (MONTPELLIER) | participant | 0.00 |
Mappa
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Obiettivo del progetto (Objective)
There is a continued need for higher compute performance: scientific grand challenges, engineering, geophysics, bioinformatics, etc. However, energy is increasingly becoming one of the most expensive resources and the dominant cost item for running a large supercomputing facility. In fact the total energy cost of a few years of operation can almost equal the cost of the hardware infrastructure. Energy efficiency is already a primary concern for the design of any computer system and it is unanimously recognized that Exascale systems will be strongly constrained by power.nnThe analysis of the performance of HPC systems since 1993 shows exponential improvements at the rate of one order of magnitude every 3 years: One petaflops was achieved in 2008, one exaflops is expected in 2020. Based on a 20 MW power budget, this requires an efficiency of 50 GFLOPS/Watt. However, the current leader in energy efficiency achieves only 1.7 GFLOPS / Watt. Thus, a 30x improvement is required.nnIn this project, we believe that HPC systems developed from today's energy-efficient solutions used in embedded and mobile devices are the most likely to succeed. As of today, the CPUs of these devices are mostly designed by ARM. However, ARM processors have not been designed for HPC, and ARM chips have never been used in HPC systems before, leading to a number of significant challenges.nnThe Mont-Blanc project has three objectives:n- To develop a fully functional energy-efficient HPC prototype using low-power commercially available embedded technologyn- To design a next-generation HPC system together with a range of embedded technologies in order to overcome the limitations identified in the prototype systemn- To develop a portfolio of exascale applications to be run on this new generation of HPC systems.nnThis will produce a new type of computer architecture capable of setting future global HPC standards that will provide Exascale performance using 15 to 30 times less energy.