ROMOL
Riding on Moore's Law
| Coordinatore | BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION
Spiacenti, non ci sono informazioni su questo coordinatore. Contattare Fabio per maggiori infomrazioni, grazie. |
| Nazionalità Coordinatore | Spain [ES] |
| Totale costo | 2˙356˙467 € |
| EC contributo | 2˙356˙467 € |
| Programma | FP7-IDEAS-ERC
Specific programme: "Ideas" implementing the Seventh Framework Programme of the European Community for research, technological development and demonstration activities (2007 to 2013) |
| Code Call | ERC-2012-ADG_20120216 |
| Funding Scheme | ERC-AG |
| Anno di inizio | 2013 |
| Periodo (anno-mese-giorno) | 2013-04-01 - 2018-03-31 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION
Organization address
address: Calle Jordi Girona 31 contact info |
ES (BARCELONA) | hostInstitution | 2˙356˙467.00 |
| 2 |
BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION
Organization address
address: Calle Jordi Girona 31 contact info |
ES (BARCELONA) | hostInstitution | 2˙356˙467.00 |
Mappa
Word cloud
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Obiettivo del progetto (Objective)
'The most common interpretation of Moore's Law is that the number of components on a chip and accordingly the computer performance doubles every two years. At the end of the 20th century, when clock frequencies stagnated at ~3 GHz, and instruction level parallelism reached the phase of diminishing returns, industry turned towards multiprocessors, and thread level parallelism. However, too much of the technological complexity of multicore architectures is exposed to the programmers, leading to a software development nightmare. We propose a radically new concept of parallel computer architectures, using a higher level of abstraction, Instead of expressing algorithms as a sequence of instruction, we will group instructions into higher-level tasks that will be automatically managed by the architecture, much in the same way superscalar processors managed instruction level parallelism. We envision a holistic approach where the parallel architecture is partially implemented as a software runtime, and the reminder in hardware. The hardware gains the freedom to deliver performance at the expense of additional complexity, as long as it provides the required support primitives for the runtime software to hide complexity from the programmer. Moreover, it offers a single solution that could solve most of the problems we encounter in the current approaches: handling parallelism, the memory wall, the power wall, and the reliability wall in a wide range of application domains from mobile up to supercomputers . We will focus our research on a most efficient form of multicore architecture coupled with vector accelerators for exploiting both thread and data level parallelism. All together, this novel approach toward future parallel architectures is the way to ensure continued performance improvements, getting us out of the technological mess that computers have turned into, once more riding on Moore's Law.'