Explore the words cloud of the FPGA Accelerators project. It provides you a very rough idea of what is the project "FPGA Accelerators" about.
The following table provides information about the project.
BILKENT UNIVERSITESI VAKIF
|Coordinator Country||Turkey [TR]|
|Total cost||145˙845 €|
|EC max contribution||145˙845 € (100%)|
1. H2020-EU.1.3.2. (Nurturing excellence by means of cross-border and cross-sector mobility)
|Duration (year-month-day)||from 2016-04-01 to 2018-03-31|
Take a look of project's partnership.
|1||BILKENT UNIVERSITESI VAKIF||TR (BILKENT ANKARA)||coordinator||145˙845.00|
It is reported that data centers today consume up to 3 percent of the global electricity usage. This is expected to increase in the upcoming years as the amount of data processed in the cloud increases substantially. An effective way for data centers to achieve better performance and energy efficiency is to perform computation on specialized processing elements. Field programmable gate arrays (FPGAs) enable customization of logic after manufacturing to achieve better energy efficiency compared to general purpose processors. Today, prominent hardware and software companies are investing in data center solutions that integrate FPGAs with CPUs, and significant energy consumption and performance improvements have been demonstrated for several data center applications. However, the main barrier for wide spread adoption of FGPAs in data centers is the cost of programming, which typically requires months of development time by hardware designers. This makes it unaffordable for small-to-medium software companies to effectively utilize the available FPGAs. The purpose of this project is to lower this barrier for emerging graph analytics applications for knowledge discovery and machine learning. The basic idea is to use an abstract interface that allows a domain expert to describe an application as a set of serial functions defined per vertex and/or edge. We propose a customizable implementation template that automatically maps the abstract user functions to massively parallel FPGA implementations. The proposed template will hide from users many low level implementation details such as parallelization, pipelining, synchronization, memory access optimization, race and deadlock avoidance, etc. This will help bridge the gap between high level application descriptions and costly hardware implementations. Our preliminary architecture simulations have shown that the proposed graph processors can achieve significantly better energy efficiency than general purpose processors.
|year||authors and title||journal||last update|
Muhammet Mustafa Ozdal
Emerging Accelerator Platforms for Data Centers
published pages: 47-54, ISSN: 2168-2356, DOI: 10.1109/mdat.2017.2779742
|IEEE Design & Test 35/1||2019-06-13|
Andrey Ayupov, Serif Yesil, Muhammet Mustafa Ozdal, Taemin Kim, Steven Burns, Ozcan Ozturk
A Template-Based Design Methodology for Graph-Parallel Hardware Accelerators
published pages: 420-430, ISSN: 0278-0070, DOI: 10.1109/tcad.2017.2706562
|IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 37/2||2019-06-13|
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The information about "FPGA ACCELERATORS" are provided by the European Opendata Portal: CORDIS opendata.
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