NeuRAM3 SIGNED
NEUral computing aRchitectures in Advanced Monolithic 3D-VLSI nano-technologies
Total Cost €
0EC-Contrib. €
0Partnership
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Explore the words cloud of the NeuRAM3 project. It provides you a very rough idea of what is the project "NeuRAM3" about.
Project "NeuRAM3" data sheet
The following table provides information about the project.
| Coordinator |
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Organization address contact info |
| Coordinator Country | France [FR] |
| Project website | http://www.neuram3.eu/ |
| Total cost | 4˙181˙015 € |
| EC max contribution | 3˙216˙150 € (77%) |
| Programme |
1. H2020-EU.2.1.1. (INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT)) |
| Code Call | H2020-ICT-2015 |
| Funding Scheme | RIA |
| Starting year | 2016 |
| Duration (year-month-day) | from 2016-01-01 to 2019-06-30 |
Partnership
Take a look of project's partnership.
| # | ||||
|---|---|---|---|---|
| 1 | COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES | FR (PARIS 15) | coordinator | 1˙196˙073.00 |
| 2 | AGENCIA ESTATAL CONSEJO SUPERIOR DEINVESTIGACIONES CIENTIFICAS | ES (MADRID) | participant | 483˙220.00 |
| 3 | STMICROELECTRONICS SA | FR (MONTROUGE) | participant | 426˙000.00 |
| 4 | CONSIGLIO NAZIONALE DELLE RICERCHE | IT (ROMA) | participant | 400˙590.00 |
| 5 | JACOBS UNIVERSITY BREMEN GGMBH | DE (BREMEN) | participant | 303˙687.00 |
| 6 | INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM | BE (LEUVEN) | participant | 251˙578.00 |
| 7 | STICHTING IMEC NEDERLAND | NL (EINDHOVEN) | participant | 155˙000.00 |
| 8 | IBM RESEARCH GMBH | CH (RUESCHLIKON) | participant | 0.00 |
| 9 | UNIVERSITAT ZURICH | CH (ZURICH) | participant | 0.00 |
Map
Project objective
We propose to fabricate a chip implementing a neuromorphic architecture that supports state-of-the-art machine learning algorithms and spike-based learning mechanisms. With respect to its physical architecture this chip will feature an ultra low power, scalable and highly configurable neural architecture that will deliver a gain of a factor 50x in power consumption on selected applications compared to conventional digital solutions; and fabricated in Fully- Depleted Silicon on Insulator (FDSOI) at 28nm design rules. In parallel the project will be validating the modules to realise RRAM synapses both planar and in a 3D monolithic structure. We will complete this vision and develop complementary technologies that will allow to address the full spectrum of applications from mobile/autonomous objects to high performance computing coprocessing, by realising (1) a technology to implement on-chip learning, using native adaptive characteristics of electronic synaptic elements; and (2) a scalable platform to interconnect multiple neuromorphic processor chips to build large neural processing systems. The neuromorphic computing system will be developed jointly with advanced neural algorithms and computational architectures for online adaptation, learning, and high-throughput on-line signal processing, delivering 1. an ultra-low power massively parallel non von Neumann computing platform with non-volatile nano-scale devices that support on-line learning mechanisms 2. a programming toolbox of algorithms and data structures tailored to the specific constraints and opportunities of the physical architecture; 3. an array of fundamental application demonstrations instantiating the basic classes of signal processing tasks. The neural chip will validate the concept and be a first step to develop a European technology platform addressing from ultra-low power data processing in autonomous systems (Internet of Things) to energy efficient large data processing in servers and networks.
Deliverables
| Physical Level and Computational Level benchmarking. | Documents, reports | 2020-01-28 10:21:32 |
| Toolbox of algorithms and computational architecture building blocks. | Other | 2020-01-28 10:21:32 |
| Joint publication on hardware compatible recurrent neural network architecture. | Documents, reports | 2020-01-28 10:21:32 |
| Report on spike-based learning circuits suitable for RRAM technologies. | Documents, reports | 2020-01-28 10:21:31 |
| Design ready for tape-out of the FDSOI 28nm multi-core spiking neural network chip. | Other | 2020-01-28 10:21:31 |
| Project web-site on line with public and restricted areas | Other | 2020-01-28 10:21:31 |
| Report on the characteristics of TFT’s as interconnects for a Global Synapse Chips | Documents, reports | 2020-01-28 10:21:31 |
| Report on digital spike-based computing circuits suitable for RRAM technologies | Documents, reports | 2020-01-28 10:21:31 |
| Process description for the integration of RRAM technology in 28nm FDSOI BEOL, as input for WP 3 | Documents, reports | 2020-01-28 10:21:31 |
| Electrical characterization of 1T-1R RRAM cell as input for compact modeling for WP 2 | Documents, reports | 2020-01-28 10:21:31 |
Take a look to the deliverables list in detail: detailed list of NeuRAM3 deliverables.
Publications
| year | authors and title | journal | last update |
|---|---|---|---|
| 2018 |
Adarsha Balaji, Federico Corradi, Anup Das, Sandeep Pande, Siebren Schaafsma, Francky Catthoor Power-Accuracy Trade-Offs for Heartbeat Classification on Neural Networks Hardware published pages: 508-519, ISSN: 1546-1998, DOI: 10.1166/jolpe.2018.1582 |
Journal of Low Power Electronics 14/4 | 2020-01-28 |
| 2017 |
Ning Qiao, Chiara Bartolozzi, Giacomo Indiveri An Ultralow Leakage Synaptic Scaling Homeostatic Plasticity Circuit With Configurable Time Scales up to 100 ks published pages: 1271-1277, ISSN: 1932-4545, DOI: 10.1109/tbcas.2017.2754383 |
IEEE Transactions on Biomedical Circuits and Systems 11/6 | 2020-01-28 |
| 2018 |
Saber Moradi, Ning Qiao, Fabio Stefanini, Giacomo Indiveri A Scalable Multicore Architecture With Heterogeneous Memory Structures for Dynamic Neuromorphic Asynchronous Processors (DYNAPs) published pages: 106-122, ISSN: 1932-4545, DOI: 10.1109/TBCAS.2017.2759700 |
IEEE Transactions on Biomedical Circuits and Systems 12/1 | 2020-01-28 |
| 2018 |
Raphaela Kreiser, Dora Aathmani, Ning Qiao, Giacomo Indiveri, Yulia Sandamirskaya Organizing Sequential Memory in a Neuromorphic Device Using Dynamic Neural Fields published pages: , ISSN: 1662-453X, DOI: 10.3389/fnins.2018.00717 |
Frontiers in Neuroscience 12 | 2020-01-28 |
| 2017 |
Manu V Nair, Lorenz K Muller, Giacomo Indiveri A differential memristive synapse circuit for on-line learning in neuromorphic computing systems published pages: 35003, ISSN: 2399-1984, DOI: 10.1088/2399-1984/aa954a |
Nano Futures 1/3 | 2020-01-28 |
| 2019 |
F. Hadaeghi Neuromorphic Electronic Systems for Reservoir Computing published pages: , ISSN: , DOI: |
Reservoir Computing: Theory, Physical Implementations and Applications | 2020-01-28 |
| 2018 |
X. He, H. Jaeger Overcoming Catastrophic Interference using Conceptor-Aided Backpropagation published pages: , ISSN: , DOI: |
Proc. International Conference on Learning Representations 2018 (ICLR 2018) | 2020-01-28 |
| 2019 |
S Brivio, D Conti, M V Nair, J Frascaroli, E Covi, C Ricciardi, G Indiveri, S Spiga Extended memory lifetime in spiking neural networks employing memristive synapses with nonlinear conductance dynamics published pages: 15102, ISSN: 0957-4484, DOI: 10.1088/1361-6528/aae81c |
Nanotechnology 30/1 | 2020-01-28 |
| 2017 |
Francky Catthoor, Srinjoy Mitra, Anup Das and Siebren Schaafsma Very Large Scale Neuromorphic Systems For Biological Signal Processing published pages: , ISSN: , DOI: |
CMOS Circuits for Biological Sensing and Processing Systems | 2020-01-28 |
| 2017 |
Prathyusha Adiraju Exploration of general purpose interface for spiking-based application simulator published pages: , ISSN: , DOI: |
2020-01-28 | |
| 2017 |
S. Brivio, S. Spiga Stochastic circuit breaker network model for bipolar resistance switching memories published pages: 1-13, ISSN: 1569-8025, DOI: 10.1007/s10825-017-1055-y |
Journal of Computational Electronics | 2020-01-28 |
| 2017 |
C. Mohan, T. Serrano-Gotarredona, E. Vianello, L. Perniolla, C. Reita, J.M. de la Rosa, B. Linares-Barranco On the Use of Offset Calibration Techniques for Low-Power Memristor Arrays Read-Out published pages: , ISSN: , DOI: |
International Conference on Memristive Materials, Devices & Systems (MEMRISYS 2017) biannual | 2020-01-28 |
| 2018 |
Jacopo Frascaroli, Stefano Brivio, Erika Covi, Sabina Spiga Evidence of soft bound behaviour in analogue memristive devices for neuromorphic computing published pages: , ISSN: 2045-2322, DOI: 10.1038/s41598-018-25376-x |
Scientific Reports 8/1 | 2020-01-28 |
| 2017 |
Hadaeghi, F. and He, X. and Jaeger, H. Unconventional Information Processing Systems, Novel Hardware: A Tour d’Horizon published pages: , ISSN: , DOI: |
2020-01-28 | |
| 2017 |
Evangelos Stromatias, Miguel Soto, Teresa Serrano-Gotarredona, Bernabé Linares-Barranco An Event-Driven Classifier for Spiking Neural Networks Fed with Synthetic or Dynamic Vision Sensor Data published pages: , ISSN: 1662-453X, DOI: 10.3389/fnins.2017.00350 |
Frontiers in Neuroscience 11 | 2020-01-28 |
| 2017 |
Yuefeng Wu Exploration of segmented bus architecture for neuromorphic computing published pages: , ISSN: , DOI: |
2020-01-28 | |
| 2017 |
Stefano Brivio, Jacopo Frascaroli, Sabina Spiga Role of Al doping in the filament disruption in HfO2 resistance switches published pages: , ISSN: 0957-4484, DOI: 10.1088/1361-6528/aa8013 |
Nanotechnology | 2020-01-28 |
| 2017 |
He, Xu and Jaeger, Herbert Overcoming Catastrophic Interference by Con-ceptors published pages: , ISSN: , DOI: |
2020-01-28 | |
| 2018 |
E Covi, R George, J Frascaroli, S Brivio, C Mayr, H Mostafa, G Indiveri, S Spiga Spike-driven threshold-based learning with memristive synapses and neuromorphic silicon neurons published pages: 344003, ISSN: 0022-3727, DOI: 10.1088/1361-6463/aad361 |
Journal of Physics D: Applied Physics 51/34 | 2020-01-28 |
| 2019 |
Fatemeh Hadaeghi, Herbert Jaeger Computing optimal discrete readout weights in reservoir computing is NP-hard published pages: 233-236, ISSN: 0925-2312, DOI: 10.1016/j.neucom.2019.02.009 |
Neurocomputing 338 | 2020-01-28 |
| 2019 |
S Brivio, D Conti, M V Nair, J Frascaroli, E Covi, C Ricciardi, G Indiveri, S Spiga Extended memory lifetime in spiking neural networks employing memristive synapses with nonlinear conductance dynamics published pages: 15102, ISSN: 0957-4484, DOI: 10.1088/1361-6528/aae81c |
Nanotechnology 30/1 | 2020-01-28 |
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