DPMP
Dependable Performance on Many-Thread Processors
| Coordinatore | UNIVERSITEIT GENT
Spiacenti, non ci sono informazioni su questo coordinatore. Contattare Fabio per maggiori infomrazioni, grazie. |
| Nazionalità Coordinatore | Belgium [BE] |
| Totale costo | 1˙389˙000 € |
| EC contributo | 1˙389˙000 € |
| Programma | FP7-IDEAS-ERC
Specific programme: "Ideas" implementing the Seventh Framework Programme of the European Community for research, technological development and demonstration activities (2007 to 2013) |
| Code Call | ERC-2010-StG_20091028 |
| Funding Scheme | ERC-SG |
| Anno di inizio | 2010 |
| Periodo (anno-mese-giorno) | 2010-10-01 - 2016-09-30 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
UNIVERSITEIT GENT
Organization address
address: SINT PIETERSNIEUWSTRAAT 25 contact info |
BE (GENT) | hostInstitution | 1˙389˙000.00 |
| 2 |
UNIVERSITEIT GENT
Organization address
address: SINT PIETERSNIEUWSTRAAT 25 contact info |
BE (GENT) | hostInstitution | 1˙389˙000.00 |
Mappa
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Obiettivo del progetto (Objective)
'Contemporary microprocessors seek at improving performance through thread-level parallelism by co-executing multiple threads on a single microprocessor chip. Projections suggest that future processors will feature multiple tens to hundreds of threads, hence called many-thread processors. Many-thread processors, however, lead to non-dependable performance: co-executing threads affect each other s performance in unpredictable ways because of resource sharing across threads. Failure to deliver dependable performance leads to missed deadlines, priority inversion, unbalanced parallel execution, etc., which will severely impact the usage model and the performance growth path for many important future and emerging application domains (e.g., media, medical, datacenter).
DPMP envisions that performance introspection using a cycle accounting architecture that tracks per-thread performance, will be the breakthrough to delivering dependable performance in future many-thread processors. To this end, DPMP will develop a hardware cycle accounting architecture that estimates single-thread progress during many-thread execution. The ability to track per-thread progress enables system software to deliver dependable performance by assigning hardware resources to threads depending on their relative progress. Through this cooperative hardware-software approach, this project addresses a fundamental problem in multi-threaded ad multi/many-core processing.'