CALDERA

Clustered Atomic Layer Deposition for Emerging micRoelectonic Applications

 Coordinatore INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW 

 Organization address address: Kapeldreef 75
city: LEUVEN
postcode: 3001

contact info
Titolo: Ms.
Nome: Christine
Cognome: Van Houtven
Email: send email
Telefono: +32 16 28 1613

 Nazionalità Coordinatore Belgium [BE]
 Totale costo 50˙000 €
 EC contributo 50˙000 €
 Programma FP7-PEOPLE
Specific programme "People" implementing the Seventh Framework Programme of the European Community for research, technological development and demonstration activities (2007 to 2013)
 Code Call FP7-PEOPLE-2010-RG
 Funding Scheme MC-IRG
 Anno di inizio 2011
 Periodo (anno-mese-giorno) 2011-03-01   -   2013-02-28

 Partecipanti

# participant  country  role  EC contrib. [€] 
1    INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW

 Organization address address: Kapeldreef 75
city: LEUVEN
postcode: 3001

contact info
Titolo: Ms.
Nome: Christine
Cognome: Van Houtven
Email: send email
Telefono: +32 16 28 1613

BE (LEUVEN) coordinator 50˙000.00

Mappa


 Word cloud

Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.

combination    dielectric    tools    interfaces    defect    tool    free    materials    al    channel    ald    interface    surfaces    surface    air    silicon    gaas    deposition    clustered    prior    gate    situ    native    before    drive    defects   

 Obiettivo del progetto (Objective)

'A less-well known aspect of Moore's law is the need for increased drive current of the transistors. In addition to traditional dimensional scaling, recent work to improve the drive current is increasingly based on alternative materials with higher carrier mobility. When replacing silicon with III-V compound semiconductors as the channel material in CMOS devices, the main problem is the passivation of the interface between the channel and the gate dielectric due to defects created at the III-V surface by the formation of native oxides. It is important to either remove these defects or avoid their formation before the deposition of the gate dielectric to achieve acceptable electronic performance. The most promising gate dielectric for III-V materials is Al2O3 when grown by atomic layer deposition (ALD). Although ALD Al2O3 provides native-oxide-free interfaces with GaAs, the interface defect density is still much larger than on silicon and it is necessary to avoid the oxidation of the surface prior to gate dielectric deposition. Since GaAs has been reported as being deposited epitaxially by ALD, this will be a means to generate defect free surfaces. But to be effective, this must be combined with a clustered deposition of Al2O3 without any air break. The use of in-situ analysis tools in combination with a clustered deposition tool provide an ideal means to study the initial stages of ALD on III-V surfaces and the interface formation since all air exposure will be avoided. In-situ analysis during ALD has been done before, but never with a combination of analysis tools used on the same sample. Since no prior tools combining clustered ALD of both GaAs and Al2O3 and in-situ characterization techniques exist, a major part of the proposed work will be the design and the assembly of a clustered ALD deposition tool. By enabling such a combination, this project will provide the clearest insight into the growth mechanisms of ALD and of III-V interfaces to date.'

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