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ExaNoDe

European Exascale Processor Memory Node Design

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EC-Contrib. €

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Project "ExaNoDe" data sheet

The following table provides information about the project.

Coordinator
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES 

Organization address
address: RUE LEBLANC 25
city: PARIS 15
postcode: 75015
website: www.cea.fr

contact info
title: n.a.
name: n.a.
surname: n.a.
function: n.a.
email: n.a.
telephone: n.a.
fax: n.a.

 Coordinator Country France [FR]
 Project website http://exanode.eu/
 Total cost 8˙629˙247 €
 EC max contribution 8˙629˙247 € (100%)
 Programme 1. H2020-EU.1.2.2. (FET Proactive)
 Code Call H2020-FETHPC-2014
 Funding Scheme RIA
 Starting year 2015
 Duration (year-month-day) from 2015-10-01   to  2019-06-30

 Partnership

Take a look of project's partnership.

# participants  country  role  EC contrib. [€] 
1    COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES FR (PARIS 15) coordinator 3˙041˙945.00
2    IDRYMA TECHNOLOGIAS KAI EREVNAS EL (IRAKLEIO) participant 1˙091˙500.00
3    THE UNIVERSITY OF MANCHESTER UK (MANCHESTER) participant 780˙068.00
4    BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION ES (BARCELONA) participant 568˙000.00
5    SCAPOS AG DE (SANKT AUGUSTIN) participant 524˙400.00
6    VIRTUAL OPEN SYSTEMS FR (GRENOBLE) participant 484˙375.00
7    EIDGENOESSISCHE TECHNISCHE HOCHSCHULE ZUERICH CH (ZUERICH) participant 482˙103.00
8    FRAUNHOFER GESELLSCHAFT ZUR FOERDERUNG DER ANGEWANDTEN FORSCHUNG E.V. DE (MUNCHEN) participant 372˙500.00
9    CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE CNRS FR (PARIS) participant 369˙165.00
10    FORSCHUNGSZENTRUM JULICH GMBH DE (JULICH) participant 357˙922.00
11    BULL SAS FR (LES CLAYES SOUS BOIS) participant 229˙000.00
12    ARM LIMITED UK (CAMBRIDGE) participant 203˙267.00
13    KALRAY SA FR (MONTBONNOT) participant 125˙000.00

Map

 Project objective

ExaNoDe will investigate, develop integrate and validate the building blocks (technology readiness level 5) for a highly efficient, highly integrated, multi-way, high-performance, heterogeneous compute element aimed towards exascale computing. It will build on multiple European initiatives for scalable computing, utilizing low- power processors and advanced nanotechnologies. ExaNoDe will draw heavily on the Unimem memory and system design paradigm defined within the EUROSERVER FP7 project, providing low-latency, high-bandwidth and resilient memory access, scalable to Exabyte levels.

The ExaNoDe compute element aims towards exascale compute goals through: • Integration of the most advanced low-power processors and accelerators (across scalar, SIMD, GPGPU and FPGA processing elements) supported by research and innovation in the deployment of associated nanotechnologies and in the mechanical requirements to enable the development of a high-density, high-performance integrated compute element with advanced thermal characteristics and connectivity to the next generation of system interconnect and storage; • Undertaking essential research to ensure the ExaNoDe compute element provides necessary support of HPC applications including I/O and storage virtualization techniques, operating system and semantically aware runtime capabilities and PGAS, OpenMP and MPI paradigms; • The development of a hardware emulation of interconnect to enable the evaluation of Unimem for the deployment of multiple compute elements and to leverage the potential of the ExaNoDe approach for HPC applications.

Each aspect of ExaNoDe is aligned with the goals of the ETP4HPC. The work will be steered by first-hand experience and analysis of high-performance applications and their requirements; investigations being carried out with “mini-application” abstractions and the tuning of their kernels.

 Deliverables

List of deliverables.
Final Project Press release Other 2020-03-03 14:35:51
Report on the ExaNoDe infrastructure requirements Documents, reports 2020-03-03 14:35:52
Report on the performance bottlenecks of the ExaNoDe architecture Documents, reports 2020-03-03 14:35:51
Workshop report Documents, reports 2020-03-03 14:35:52
Report on the performance opportunities of the next-generation memory systems Documents, reports 2020-03-03 14:35:51
Report on the ExaNoDe architecture design guidelines Documents, reports 2020-03-03 14:35:50
Report on the ExaNoDe miniapplications Documents, reports 2020-03-03 14:35:50
Initial Project Press Release Other 2020-03-03 14:35:50
HW-SW integration and tuning Documents, reports 2020-03-03 14:35:50
Report on the performance bottlenecks of the state-of-the-art HPC platforms Documents, reports 2020-03-03 14:35:50
Runtime systems (OmpSs, OpenStream) and communication libraries (GPI, MPI): Analysis of the hardware system characteristics and design of a preliminary software implementation. Documents, reports 2020-03-03 14:35:50
Design of the ExaNoDe Firmware [ report and initial prototype] Documents, reports 2020-03-03 14:35:50
Data Management Plan for pilot on Open Research Data Open Research Data Pilot 2020-03-03 14:35:50
Final report on Firmware and Operating System for ExaNoDe [ report and final prototype] Demonstrators, pilots, prototypes 2020-03-03 14:35:51
Operating System Support for ExaNoDe [ report and interim prototype] Documents, reports 2020-03-03 14:35:51
Runtime systems (OmpSs, OpenStream) and communication libraries (GPI, MPI): Advanced implementation customized for ExaNoDe architecture, interconnect, operating system. Documents, reports 2020-03-03 14:35:51
Project External Website, project flyer and social media presence Other 2020-03-03 14:35:52
Final tuning and evaluation results Documents, reports 2020-03-03 14:35:51
Runtime systems (OmpSs, OpenStream) and communication libraries (GPI, MPI): Final tuned implementation optimized for the delivered prototype machine. Demonstrators, pilots, prototypes 2020-03-03 14:35:51
Report and best practices on porting of the mini-applications to the ExaNoDe architecture Documents, reports 2020-03-03 14:35:52
Dissemination Strategy Document Documents, reports 2020-03-03 14:35:52

Take a look to the deliverables list in detail:  detailed list of ExaNoDe deliverables.

 Publications

year authors and title journal last update
List of publications.
2016 Francesco Beneventi, Andrea Bartolini, Pascal Vivet, Luca Benini
Thermal Analysis and Interpolation Techniques for a Logic + WideIO Stacked DRAM Test Chip
published pages: 623-636, ISSN: 0278-0070, DOI: 10.1109/tcad.2015.2474382
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 35/4 2020-03-03
2019 Milan Radulovic, Rommel Sanchez Verdejo, Paul Carpenter, Petar Radojković, Bruce Jacob, Eduard Ayguadé
PROFET: modeling system performance and energy without simulating the CPU
published pages: , ISSN: 2476-1249, DOI:
Proceedings of the ACM on Measurement and Analysis of Computing Systems Volume 3 Issue 2 2020-03-03
2017 Francesco Conti, Robert Schilling, Pasquale Davide Schiavone, Antonio Pullini, Davide Rossi, Frank Kagan Gurkaynak, Michael Muehlberghuber, Michael Gautschi, Igor Loi, Germain Haugou, Stefan Mangard, Luca Benini
An IoT Endpoint System-on-Chip for Secure and Energy-Efficient Near-Sensor Analytics
published pages: 2481-2494, ISSN: 1549-8328, DOI: 10.1109/TCSI.2017.2698019
IEEE Transactions on Circuits and Systems I: Regular Papers 64/9 2020-03-03
2018 Andrea Bartolini, Roberto Diversi, Daniele Cesarini, Francesco Beneventi
Self-Aware Thermal Management for High-Performance Computing Processors
published pages: 28-35, ISSN: 2168-2356, DOI: 10.1109/MDAT.2017.2774774
IEEE Design & Test 35/5 2020-03-03
2018 Živanovič, Darko
Memory systems for high-performance computing: the capacity and reliability implications
published pages: , ISSN: , DOI:
Tesis Doctorals en Xarxa 2020-03-03
2017 Beneventi, Francesco; Bartolini, Andrea; Cavazzoni, Carlo; Benini, Luca
Continuous learning of HPC infrastructure models using big data analytics and in-memory processing tools
published pages: 1038-1043, ISSN: , DOI: 10.3929/ethz-b-000192078
Proceedings of the 2017 Design, Automation and Test in Europe, DATE 2017 2020-03-03
2017 Richard Neill, Andi Drebes, Antoniu Pop
Fuse
published pages: 1-26, ISSN: 1544-3566, DOI: 10.1145/3148054
ACM Transactions on Architecture and Code Optimization 14/4 2020-03-03
2017 Darko Zivanovic, Milan Pavlovic, Milan Radulovic, Hyunsung Shin, Jongpil Son, Sally A. Mckee, Paul M. Carpenter, Petar Radojković, Eduard Ayguadé
Main Memory in HPC
published pages: 1-26, ISSN: 1544-3566, DOI: 10.1145/3023362
ACM Transactions on Architecture and Code Optimization 14/1 2020-03-03
2016 Andi Drebes, Jean-Baptiste Bréjon, Antoniu Pop, Karine Heydemann, Albert Cohen
Language-Centric Performance Analysis of OpenMP Programs with Aftermath
published pages: 237-250, ISSN: , DOI: 10.1007/978-3-319-45550-1_17
2020-03-03
2015 Pleiter, Dirk
JSCs Horizon 2020
published pages: , ISSN: 0302-9743, DOI:
Innovatives Supercomputing in Deutschland 13(2), 64(2015). 6 2020-03-03
2017 Francesco Conti, Daniele Palossi, Renzo Andri, Michele Magno, Luca Benini
Accelerated Visual Context Classification on a Low-Power Smartwatch
published pages: 1-12, ISSN: 2168-2291, DOI: 10.1109/thms.2016.2623482
IEEE Transactions on Human-Machine Systems 2020-03-03
2019 Przemyslaw Mroszczyk, John Goodacre, Vasilis F. Pavlidis
Energy Efficient Flash ADC with PVT Variability Compensation through Advanced Body Biasing
published pages: 1-1, ISSN: 1549-7747, DOI: 10.1109/tcsii.2019.2891580
IEEE Transactions on Circuits and Systems II: Express Briefs 2020-03-03

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