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GREAT SIGNED

heteroGeneous integRated magnetic tEchnology using multifunctional standardized sTack (MSS)

Total Cost €

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EC-Contrib. €

0

Partnership

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 GREAT project word cloud

Explore the words cloud of the GREAT project. It provides you a very rough idea of what is the project "GREAT" about.

2020    baseline    mtjs    self    speed    advisory    cell    board    final    cea    receivers    co    interconnected    moderate    mss    things    fast    storage    components    communication    rf    adapting    simulation    architectures    paving    billion    density    fabrication    comprising    sensing    multifunctional    multiple    connected    functions    magnetic    smart    decrease    consumption    mobile    jointly    internet    sensors    communicating    mtj    architecture    autonomy    m2m    socs    single    stack    dense    simpler    chip    tackle    endurance    provides    autonomous    wireless    write    iot    volatility    infinite    outputs    cmos    miniaturization    integrating    performances    heterogeneous    ultra    storing    5d    strep    integration    battery    memory    representative    chips    leaders    stt    objects    solutions    platform    ip    power    circuits    integrate    read    led    computing    monolithic    logic    technologies    separate    bottleneck    operated    standardized   

Project "GREAT" data sheet

The following table provides information about the project.

Coordinator
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES 

Organization address
address: RUE LEBLANC 25
city: PARIS 15
postcode: 75015
website: www.cea.fr

contact info
title: n.a.
name: n.a.
surname: n.a.
function: n.a.
email: n.a.
telephone: n.a.
fax: n.a.

 Coordinator Country France [FR]
 Project website http://www.great-research.eu
 Total cost 4˙539˙001 €
 EC max contribution 4˙539˙001 € (100%)
 Programme 1. H2020-EU.2.1.1. (INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT))
 Code Call H2020-ICT-2015
 Funding Scheme RIA
 Starting year 2016
 Duration (year-month-day) from 2016-01-01   to  2019-06-30

 Partnership

Take a look of project's partnership.

# participants  country  role  EC contrib. [€] 
1    COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES FR (PARIS 15) coordinator 922˙833.00
2    TOWER SEMICONDUCTOR LTD IL (MIGDAL HAEMEK) participant 994˙807.00
3    CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE CNRS FR (PARIS) participant 775˙549.00
4    KARLSRUHER INSTITUT FUER TECHNOLOGIE DE (KARLSRUHE) participant 708˙375.00
5    Singulus Technologies AG DE (KAHL AM MAIN) participant 335˙573.00
6    TECHNISCHE UNIVERSITAET DRESDEN DE (DRESDEN) participant 318˙750.00
7    UNIVERSITATEA TRANSILVANIA DIN BRASOV RO (BRASOV) participant 236˙562.00
8    TOPLINK INNOVATION FR (La Seyne sur Mer) participant 130˙000.00
9    EVADERIS FR (GRENOBLE) participant 116˙550.00

Map

 Project objective

The interest for developing smart systems based on interconnected objects is growing fast (50 billion objects connected in 2020). The main components of “Internet of Things” (IoT) devices are autonomous battery-operated smart embedded systems comprising communication circuits, sensors, computing/processing devices and storage. The key requirements are ultra-low power, high processing capabilities, fast/dense storage, wireless communication, heterogeneous integration, and autonomy. The different functions are so far implemented in separate chips/technologies, which is a bottleneck in terms of costs and miniaturization. To tackle the key issues of monolithic heterogeneous integration, fast yet low power processing, high integration density, fast yet low power storage, the goal of the GREAT STREP project is to co-integrate multiple functions like sensors (“Sensing”), RF receivers (“Communicating”) and logic/memory (“Processing/Storing”) together within CMOS by adapting the STT-MTJs (Magnetic devices) to a single baseline technology. This lead to a unique STT-MTJ cell technology called Multifunctional Standardized (MTJ) Stack (MSS), paving the way to 2.5D self-integrated heterogeneous architectures . The major outputs of GREAT are the technology and the architecture platform for IoT SoCs which provides better integration of embedded & mobile communication systems and a significant decrease of their power consumption. Based on the STT unique set of performances (non-volatility, high speed, infinite endurance and moderate read/write power), GREAT will achieve the same goal as heterogeneous integration of devices but in a much simpler way. The project final objectives are: fabrication of an advanced MSS technology test chip jointly with a system-level simulation and design of a representative M2M IoT platform integrating MSS. The consortium is composed of 9 EU partners led by CEA and of an Advisory Board comprising leaders in IP solutions, IoT, and mobile technologies.

 Deliverables

List of deliverables.
2nd Community Periodic Contribution Documents, reports 2019-11-08 11:11:31
2nd Management Periodic Report Documents, reports 2019-11-08 11:11:41
Final IP documentation Documents, reports 2019-11-08 11:12:24
Consolidated standard cell library Other 2019-11-08 11:12:20
2nd Dissemination & Promotion of project results Documents, reports 2019-11-08 11:11:22
One publication on micromagnetic modelling Websites, patent fillings, videos etc. 2019-05-30 17:19:26
1st Management Periodic Report Documents, reports 2019-05-30 17:19:28
Project Presentation Websites, patent fillings, videos etc. 2019-05-30 17:19:27
Report about demonstration of the sensor functionality using the MSS stack Documents, reports 2019-05-30 17:19:17
Report about demonstration of RF functionality using the MSS stack Documents, reports 2019-05-30 17:19:23
Management plan Documents, reports 2019-05-30 17:19:12
Report about demonstration of the memory functionality using the MSS stack Documents, reports 2019-05-30 17:19:21
GREAT website Websites, patent fillings, videos etc. 2019-05-30 17:19:27
Magnetic technology files and integration in the design suite for the physical verifications Other 2019-05-30 17:19:26
Consolidated VerilogA model of the magnetic device, for optimized design Other 2019-05-30 17:19:21
Validation of the first test chip for each IP block. Documents, reports 2019-05-30 17:19:19
Report on Ø300mm wafer processing methodology, WiW and WtW uniformity Documents, reports 2019-05-30 17:19:31
Report on hybrid memory hierarchy and processor architecture design techniques providing density, performance, low power and resilience Documents, reports 2019-05-30 17:19:21
First VerilogA model of the magnetic device to initiate the design steps Other 2019-05-30 17:19:20
1st Community Periodic Contribution Documents, reports 2019-05-30 17:19:28

Take a look to the deliverables list in detail:  detailed list of GREAT deliverables.

 Publications

year authors and title journal last update
List of publications.
2018 A. Chavent, V. Iurchuk, L.Tillie, Y. Bel, L. Vila, U. Ebels R. Sousa B. Dieny, G. di Pendina, G. Prenat, J. Langer, J. Wrona, I. L. Prejbeanu
Multifunctional magnetic tunnel junction standardized stack as universal spintronic technology for IoT
published pages: , ISSN: , DOI:
Special MRAM poster session at IEDM, poster presentation 2019-10-29
2019 Antoine Chavent, Vadym Iurchuk, Luc Tillie, Yoann Bel, Nathalie Lamard, Laurent Vila, Ursula Ebels, Ricardo C. Sousa, Bernard Dieny, Gregory Di Pendina, Guillaume Prenat, Juergen Langer, Jerzy Wrona, Ioan Lucian Prejbeanu
A multifunctional standardized MTJ stack embedding sensor, memory and oscillator functionalities
published pages: , ISSN: , DOI:
Oral presentation at JEMS 2019 2019-10-29
2019 Guillaume Patrigeon, Pascal Benoit, Lionel Torres, Sophiane Senni, Guillaume Prenat, Gregory Di Pendina
Design and Evaluation of a 28-nm FD-SOI STT-MRAM for Ultra-Low Power Microcontrollers
published pages: 58085-58093, ISSN: 2169-3536, DOI: 10.1109/ACCESS.2019.2906942
IEEE Access 7 2019-09-02
2019 Ma, R.; Tibenszky, Z.; Kreißig, M.; Ellinger, F.
A 0.41 mW Band-Tunable 6th-Order IF Bandpass Filter with 40ns Settling Time in 45nm CMOS SOI
published pages: , ISSN: , DOI:
2019-09-02
2018 Ma, R.; Kreißig, M.; Ellinger, F.
A Fast Switchable and Band-Tunable 5-7.5 GHz LNA in 45nm CMOS SOI Technology
published pages: , ISSN: , DOI:
2019-09-02
2018 I. Shankhour, J. Mohdad, F. Mailly and P. Nouet
Post-fabrication soft trimming of resistive sensors
published pages: , ISSN: , DOI:
2018 Symposium on Design, Test, Integration & Packaging of MEMS and MOEMS (DTIP), Roma, 2018, pp. 1-4 2019-09-02
2019 Patrigeon , Guillaume; Leloup , Paul; Benoit , Pascal; Torres , Lionel
FlexNode: a reconfigurable Internet of Things node for design evaluation
published pages: , ISSN: , DOI:
SAS: Sensors Applications Symposium 7 2019-09-02
2017 P. Nouet
Objets Communicants pour leS EnvironnementS et le Vivant
published pages: , ISSN: , DOI:
3 et 4 juillet 2017 2019-06-18
2017 Sophiane Senni, Lionel Torres, Pascal Benoit, Abdoulaye Gamatie, Gilles Sassatelli
Normally-Off Computing and Checkpoint/Rollback for Fast, Low-Power and Reliable Devices
published pages: 1-1, ISSN: 1949-307X, DOI: 10.1109/LMAG.2017.2712780
IEEE Magnetics Letters 2017-07-19 2019-06-18
2016 J. Wrona, J. Langer, S. Tibus, B. Ocker
High temperature stable bottom pinned perpendicular magnetic tunnel junctions (poster)
published pages: , ISSN: , DOI:
IEDM special poster session on MRAM 2019-06-18
2017 Alexandru Atitoaie(1), Marius Volmer(1), Liliana Buda-Prejbeanu(2,3,4), Ursula Ebels(2,3,4), Ioana Firastrau(1), (1)Transilvania University of Brasov, 500036, Brasov, Romania, (2)Univ. Grenoble Alpes, F-38000, Grenoble, France, (3)CEA, INAC – SPINTEC, F-38000, Grenoble, France, (4) CNRS, SPINTEC, F-38000, Grenoble, France
Shape effects on magnetization states of fully perpendicular spin transfer torque nano-oscillators (poster)
published pages: , ISSN: , DOI:
11th International Symposium on Hysteresis Modeling and Micromagnetism 2019-06-18
2017 Lionel Torres, Sophiane Senni
\"\"\"Embedded MRAM to HPC Computing\"\". Presentation of the GREAT activities during this workshop\"
published pages: , ISSN: , DOI:
May 2017 2019-06-18
2017 Sophiane Senni, Lionel Torres, Gilles Sassatelli, Abdoulaye Gamatie
Non-Volatile Processor Based on MRAM for Ultra-Low-Power IoT Devices
published pages: 1-23, ISSN: 1550-4832, DOI: 10.1145/3001936
ACM Journal on Emerging Technologies in Computing Systems 13/2 2019-06-18
2017 Odilia Coi, Guillaume Patrigeon, Sophiane Senni, Lionel Torres, Pascal Benoit
A novel SRAM - STT-MRAM hybrid cache implementation improving cache performance
published pages: , ISSN: , DOI:
IEEE/ACM International Symposium on Nanoscale Architectures July 2017 2019-06-18
2017 L. Torres
\"Speaker at InMRAM 2017: introductory Course on Magnetic Random Access Memory – Talk based on the GREAT Results \"\"Beyond MRAM - CMOS/Mag Integrated Circuit\"\"\"
published pages: , ISSN: , DOI:
3-5 july 2017 2019-06-18
2016 Jürgen Langer
High Volume Production of pTMR Layer Stacks for MRAM and Sensor Applications (invited oral presentation)
published pages: , ISSN: , DOI:
Fraunhofer IPMS - CNT Industry Partner Day Innovative: Modules for IoT 2019-06-18
2017 Sophiane Senni, Thibaud Delobelle, Odilia Coi, Pierre-Yves Peneau, Lionel Torres, Abdoulaye Gamatie, Pascal Benoit and Gilles Sassatelli
Embedded Systems to High Performance Computing using STT-MRAM
published pages: , ISSN: 1558-1101, DOI: 10.23919/DATE.2017.7927046
IEEE DATE 2017 Conference March 2017 2019-06-18
2016 J. Wrona, J. Langer, S. Tibus, B. Ocker, J. Kanak, M. Cecot, T. Stobiecki
Effect of bottom electrode smoothness on tunnel magnetoresistance in top pinned perpendicular magnetic tunnel junctions (poster)
published pages: , ISSN: , DOI:
13th Joint MMM-Intermag Conference 2019-06-18
2017 Chatterjee J, Sousa R, Auffret S and Dieny B.
Dramatic improvement of tunneling magnetoresistance and thermal stability factor of STT-MRAM cells by replacing Ta with W/Ta cap layers (oral presentation)
published pages: , ISSN: , DOI:
IEEE International Magnetics Conference INTERMAG Europe 2019-06-18
2017 LIRMM & KIT (2 papers accepted)
Organisation of Special session at DATE Conference : Organisation of the Special session about « Hot Topic Session: Spintronics-based Computing » at IEEE DATE Conference.
published pages: , ISSN: , DOI:
2019-06-18
2017 I. L. Prejbeanu, R.C. Sousa, B. Dieny
MAGNETIC RANDOM ACCESS MEMORIES: STATUS AND ROADMAP (invited talk)
published pages: , ISSN: , DOI:
THE 9th INTERNATIONAL CONFERENCE ON ADVANCED MATERIALS, ROCAM 2017 2019-06-18
2016 Lionel Torres
\"\"\"Processor Architecture Based on MRAM\"\". Presentation to the emerging technologies days of the club EEA\"
published pages: , ISSN: , DOI:
October 2016 2019-06-18
2017 I. L. Prejbeanu, A. Timopheev, M. Miron, G. Gaudin, B. Lacoste, T. Devolder, M. Marins de Castro, R. C. Sousa, L. D. Buda-Prejbeanu, S. Auffret, U. Ebels, B. Rodmacq, B. Dieny
Ultrafast sub-ns MRAM concepts for cache applications (invited talk)
published pages: , ISSN: , DOI:
Joint York-Tohoku-Kaiserslautern Symposium on spintronics 2019-06-18
2017 Alexandru Atitoaie(1), Marius Volmer(1), Liliana Buda-Prejbeanu(2,3,4), Ursula Ebels(2,3,4), Ioana Firastrau(1), (1)Transilvania University of Brasov, 500036, Brasov, Romania, (2)Univ. Grenoble Alpes, F-38000, Grenoble, France, (3)CEA, INAC – SPINTEC, F-38000, Grenoble, France, (4) CNRS, SPINTEC, F-38000, Grenoble, France
Phase diagrams study of spin transfer torque nano-oscillators based on fully perpendicular magnetic tunnel junctions (poster)
published pages: , ISSN: , DOI:
11th International Symposium on Hysteresis Modeling and Micromagnetism 2019-06-18
2017 Abdoulaye Gamatié
\"\'Simulation and Evaluation of Heterogeneous Embedded Multicore Architectures\"\". Invited talk at FETCH 2017 (Ecole d\'hiver Francophone sur les Technologies de Conception des Systèmes Embarqués Hétérogènes)\"
published pages: , ISSN: , DOI:
January 2017 2019-06-18
2017 Alexandru Atitoaie(1), Marius Volmer(1), Liliana D. Buda-Prejbeanu(2,3,4), Ursula Ebels(2,3,4), Ioana Firastrau(1), (1)Transilvania University of Brasov, 500036, Brasov, Romania, (2)Univ. Grenoble Alpes, F-38000, Grenoble, France, (3)CEA, INAC – SPINTEC, F-38000, Grenoble, France, (4) CNRS, SPINTEC, F-38000, Grenoble, France
Macrospin characterization of fully perpendicular spin transfer torque nano-oscillators (oral presentation)
published pages: , ISSN: , DOI:
The 9th International Conference on Advanced Materials, ROCAM2017 2019-06-18
2016 Sophiane Senni, Lionel Torres
\"Special joint poster session on MRAM at IEDM \"\"Non-volatile Processor Based on STT-MRAM\"\"\"
published pages: , ISSN: , DOI:
5-7 Dec 2016 2019-06-18
2016 J. Wrona, M. Zhu, J. Langer, S. Tibus, M. Smalley, S. Bennett, B. Ocker
High temperature stable bottom pinned perpendicular magnetic tunnel junctions (poster)
published pages: , ISSN: , DOI:
61th Annual Conference on Magnetism and Magnetic Materials 2019-06-18

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