Explore the words cloud of the Load Slice Core project. It provides you a very rough idea of what is the project "Load Slice Core" about.
The following table provides information about the project.
|Coordinator Country||Belgium [BE]|
|Total cost||2˙499˙500 €|
|EC max contribution||2˙499˙500 € (100%)|
1. H2020-EU.1.1. (EXCELLENT SCIENCE - European Research Council (ERC))
|Duration (year-month-day)||from 2018-01-01 to 2022-12-31|
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The ideal processor building block is a power and cost-efficient core that can maximize the extraction of memory hierarchy parallelism, a combination that neither traditional in-order nor out-of-order cores provide. We propose the Load Slice Core microarchitecture, a restricted out-of-order engine aimed squarely at extracting memory hierarchy parallelism, which, according to preliminary results, delivers a nearly 8 times higher performance per Watt per euro compared to an out-of-order core.
The overarching objective of this project to fully determine the potential of the Load Slice Core as a key building block for a novel multi-core processor architecture needed in light of both current and future challenges in software and hardware, including variable thread-level parallelism, managed language workloads, the importance of sequential performance, and the quest for significantly improved power and cost efficiency.
We anticipate significant improvement in multi-core performance within the available power budget and cost by combining chip-level dynamism to cope with variable thread-level parallelism along with the inherent power- and cost-efficient Load Slice Core design. If we are able to demonstrate the true value and potential of the Load Slice Core to address future hardware and software challenges, this project will have a long-lasting impact on the microprocessor industry moving forward.
|year||authors and title||journal||last update|
Lu Wang, Magnus Jahre, Almutaz Adileh, Zhiying Wang, Lieven Eeckhout
Modeling Emerging Memory-Divergent GPU Applications
published pages: 95-98, ISSN: 1556-6056, DOI: 10.1109/lca.2019.2923618
|IEEE Computer Architecture Letters 18/2||2019-08-29|
Ajeya Naithani, Josue Feliu, Almutaz Adileh, Lieven Eeckhout
Precise Runahead Execution
published pages: 71-74, ISSN: 1556-6056, DOI: 10.1109/lca.2019.2910518
|IEEE Computer Architecture Letters 18/1||2019-08-29|
Sander De Pestel, Sam Van den Steen, Shoaib Akram, Lieven Eeckhout
RPPM: Rapid Performance Prediction of Multithreaded Applications on Multicore Hardware
published pages: 183-186, ISSN: 1556-6056, DOI: 10.1109/lca.2018.2849983
|IEEE Computer Architecture Letters 17/2||2019-08-29|
Ajeya Naithani, Stijn Eyerman, Lieven Eeckhout
Optimizing Soft Error Reliability Through Scheduling on Heterogeneous Multicore Processors
published pages: 830-846, ISSN: 0018-9340, DOI: 10.1109/tc.2017.2779480
|IEEE Transactions on Computers 67/6||2019-08-29|
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