REFLECT

Rendering FPGAs to Multi-Core Embedded Computing

 Coordinatore HONEYWELL INTERNATIONAL SRO 

 Organization address city: Brno
postcode: 639 00

contact info
Titolo: Dr.
Nome: Jan
Cognome: Kubalcík
Email: send email
Telefono: +420 532 115 512
Fax: +420 532 115 001

 Nazionalità Coordinatore Czech Republic [CZ]
 Totale costo 3˙703˙578 €
 EC contributo 2˙719˙999 €
 Programma FP7-ICT
Specific Programme "Cooperation": Information and communication technologies
 Code Call FP7-ICT-2009-4
 Funding Scheme CP
 Anno di inizio 2010
 Periodo (anno-mese-giorno) 2010-01-01   -   2012-12-31

 Partecipanti

# participant  country  role  EC contrib. [€] 
1    HONEYWELL INTERNATIONAL SRO

 Organization address city: Brno
postcode: 639 00

contact info
Titolo: Dr.
Nome: Jan
Cognome: Kubalcík
Email: send email
Telefono: +420 532 115 512
Fax: +420 532 115 001

CZ (Brno) coordinator 0.00
2    ACE ASSOCIATED COMPILER EXPERTS B.V.

 Organization address address: DE RUYTERKADE 113
city: AMSTERDAM
postcode: 1011AB

contact info
Titolo: Mr.
Nome: Marius
Cognome: Schoorel
Email: send email
Telefono: +31 20 6646416

NL (AMSTERDAM) participant 0.00
3    Coreworks - Projectos de Circuitos e Sistemas Electronicos S.A.

 Organization address address: Rua Dona Estefania
city: Lisboa
postcode: 1000

contact info
Titolo: Prof.
Nome: Fernando
Cognome: Gonçalves
Email: send email
Telefono: +351 213 100 213
Fax: +351 213 546 061

PT (Lisboa) participant 0.00
4    HONEYWELL EOOD

 Organization address address: BUL HRISTOFOR COLUMB
city: SOFIA
postcode: 1528

contact info
Titolo: Mr.
Nome: Zlatko
Cognome: Petrov
Email: send email
Telefono: 33489122097

BG (SOFIA) participant 0.00
5    IMPERIAL COLLEGE OF SCIENCE, TECHNOLOGY AND MEDICINE

 Organization address address: Exhibition Road, South Kensington Campus
city: LONDON
postcode: SW7 2AZ

contact info
Titolo: Mr.
Nome: Shaun
Cognome: Power
Email: send email
Telefono: +44 207 594 8773
Fax: +44 207 594 8609

UK (LONDON) participant 0.00
6    INESC ID - INSTITUTO DE ENGENHARIA DE SISTEMAS E COMPUTADORES, INVESTIGACAO E DESENVOLVIMENTO EM LISBOA

 Organization address address: Rua Alves Redol
city: LISBOA
postcode: 1000029

contact info
Titolo: Dr.
Nome: Pedro
Cognome: Diniz
Email: send email
Telefono: +351 214 233 517
Fax: +351 214 233 252

PT (LISBOA) participant 0.00
7    Karlsruher Institut fuer Technologie

 Organization address address: Kaiserstrasse
city: Karlsruhe
postcode: 76131

contact info
Titolo: Mr.
Nome: Jens
Cognome: Becker
Email: send email
Telefono: 497216000000
Fax: 497216000000

DE (Karlsruhe) participant 0.00
8    TECHNISCHE UNIVERSITEIT DELFT

 Organization address address: Stevinweg
city: DELFT
postcode: 2628 CN

contact info
Titolo: Mr.
Nome: Dennis F.
Cognome: Van Doorn
Email: send email
Telefono: +31 15 2789344
Fax: +31 15 2781543

NL (DELFT) participant 0.00
9    UNIVERSIDADE DO PORTO

 Organization address address: PRACA GOMES TEIXEIRA
city: PORTO
postcode: 4099 002

contact info
Titolo: Prof.
Nome: Joao
Cognome: Cardoso
Email: send email
Telefono: +351 916629046
Fax: +351 22 557 4103

PT (PORTO) participant 0.00

Mappa


 Word cloud

Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.

programming    core    reconfigurable    specifications    lara    domain    performance    multiple    compilation    software    ao    mapping    cores    supplier    time    architectures   

 Obiettivo del progetto (Objective)

The relentless increase in capacity of Field-Programmable Gate-Arrays (FPGAs) makes them vehicles of choice for both prototypes and final products requiring on-chip multi-core, heterogeneous and reconfigurable systems. Multiple cores can be embedded as hard- or soft-macros, have customizable instruction sets, multiple distributed RAMs and/or configurable interconnections. Their flexibility allows them to achieve orders of magnitude better performance than conventional computing systems via customization. Programming these systems, however, is extremely cumbersome and error-prone and as a result their true potential is only achieved at an unreasonably high effort.nThis project will develop, implement and evaluate a novel compilation and synthesis system approach for FPGA-based platforms. We rely on Aspect-Oriented (AO) Specifications to covey critical domain knowledge to a mapping engine while preserving the advantages of a high-level imperative programming paradigm in early software development and portability. We leverage AO specifications and a set of transformations to generate an intermediate representation using an extensible mapping language (LARA). LARA specifications will allow the exploration of alternative architectures and run-time adaptive strategies enabling the generation of flexible hardware cores that can be easily incorporated into larger multi-core designs. We will evaluate the effectiveness of the proposed approach using partner-provided codes from the domain of audio/video processing and real-time avionics.nWe expect the technology developed here to be integrated by our industrial partners, a leading compilation tool supplier for reconfigurable systems and a worldwide solution supplier of embedded high-performance systems. The academic partners will promote human resources with technical excellence in the area of architectures and software development thus enabling the sustainability of a vibrant information technology European fabric.

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