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REMINDER SIGNED

Revolutionary embedded memory for internet of things devices and energy reduction

Total Cost €

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EC-Contrib. €

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Partnership

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Project "REMINDER" data sheet

The following table provides information about the project.

Coordinator
UNIVERSIDAD DE GRANADA 

Organization address
address: CUESTA DEL HOSPICIO SN
city: GRANADA
postcode: 18071
website: www.ugr.es

contact info
title: n.a.
name: n.a.
surname: n.a.
function: n.a.
email: n.a.
telephone: n.a.
fax: n.a.

 Coordinator Country Spain [ES]
 Total cost 4˙543˙793 €
 EC max contribution 3˙597˙418 € (79%)
 Programme 1. H2020-EU.2.1.1. (INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT))
 Code Call H2020-ICT-2015
 Funding Scheme /RIA
 Starting year 2016
 Duration (year-month-day) from 2016-01-01   to  2018-12-31

 Partnership

Take a look of project's partnership.

# participants  country  role  EC contrib. [€] 
1    UNIVERSIDAD DE GRANADA ES (GRANADA) coordinator 606˙250.00
2    COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES FR (PARIS 15) participant 761˙596.00
3    STMICROELECTRONICS S.A. FR (MONTROUGE) participant 537˙500.00
4    INSTITUT POLYTECHNIQUE DE GRENOBLE FR (GRENOBLE CEDEX 1) participant 501˙385.00
5    SURECORE LTD UK (LEEDS) participant 495˙750.00
6    UNIVERSITY OF GLASGOW UK (GLASGOW) participant 350˙000.00
7    Gold Standard Simulations ltd UK (Glasgow) participant 344˙937.00
8    IBM RESEARCH GMBH CH (RUESCHLIKON) participant 0.00
9    Korea Institute of Science and Technology KR (Seoul) participant 0.00

Mappa

 Project objective

REMINDER aims to develop an embedded DRAM solution optimized for ultra-low-power consumption and variability immunity, specifically focused on Internet of Things cut-edge devices. The objectives of REMINDER are : i) Investigation (concept, design, characterization, simulation, modelling), selection and optimization of a Floating-Body memory bit cell in terms of low power and low voltage, high reliability, robustness (variability), speed, reduced footprint and cost. ii) Design and fabrication in FDSOI 28nm (FD28) and FDSOI 14nm (FD14) technology nodes of a memory matrix based on the optimized bit-cells developed. Matrix memory subcircuits, blocks and architectures will be carefully analysed from the power-consumption point of view. In addition variability tolerant design techniques underpinned by variability analysis and statistical simulation technology will be considered. iii) Demonstration of a system on chip application using the developed memory solution and benchmarking with alternative embedded memory blocks. The eventual replacement of Si by strained Si/SiGe and III-V materials in future CMOS circuits would also require the redesign of different applications, including memory cells, and therefore we also propose the evaluation of the optimized bit cells developed in FD28 and FD14 technology nodes using these alternative materials. The fulfilment of the objectives above will also imply the development of: i) New techniques for the electrical characterization of ultimate CMOS nanometric devices. This will allow us to improve the CMOS technology by boosting device performance. ii) New behavioural models, incorporating variability effects, to reach a deep understanding of nanoelectronics devices iii) Advanced simulation tools for nanoelectronic devices for state of the art, and emerging devices. iv) Extreme low power solutions The consortium supporting this proposal is ideally balanced with 2 industrial partners, 2 SMEs, 2 research centers and 3 universities.

 Work performed, outcomes and results:  advancements report(s) 

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The information about "REMINDER" are provided by the European Opendata Portal: CORDIS opendata.

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