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De-RISC SIGNED

De-RISC: Dependable Real-time Infrastructure for Safety-critical Computer

Total Cost €

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EC-Contrib. €

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Partnership

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Project "De-RISC" data sheet

The following table provides information about the project.

Coordinator
FENT INNOVATIVE SOFTWARE SOLUTIONSSL 

Organization address
address: CAMINO VERA CIUDAD POLITECNICA DE LA INNOVACION
city: VALENCIA
postcode: 46022
website: www.fentiss.com

contact info
title: n.a.
name: n.a.
surname: n.a.
function: n.a.
email: n.a.
telephone: n.a.
fax: n.a.

 Coordinator Country Spain [ES]
 Total cost 3˙444˙625 €
 EC max contribution 2˙617˙937 € (76%)
 Programme 1. H2020-EU.3. (PRIORITY 'Societal challenges)
2. H2020-EU.2.1. (INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies)
 Code Call H2020-EIC-FTI-2018-2020
 Funding Scheme IA
 Starting year 2019
 Duration (year-month-day) from 2019-10-01   to  2022-03-31

 Partnership

Take a look of project's partnership.

# participants  country  role  EC contrib. [€] 
1    FENT INNOVATIVE SOFTWARE SOLUTIONSSL ES (VALENCIA) coordinator 743˙925.00
2    BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION ES (BARCELONA) participant 689˙000.00
3    COBHAM GAISLER AB SE (GOTEBORG) participant 685˙912.00
4    THALES SA FR (COURBEVOIE) participant 499˙100.00

Map

 Project objective

The De-RISC project addresses computer systems within the space and aviation domains. De-RISC – Dependable Real-time Infrastructure for Safety-critical Computer – is a proposed project where an international consortium will introduce a hardware and software platform based around the RISC-V ISA. The work proposed in this project is to productize a multi-core RISC-V system-on-chip design already owned by CG and to port the XtratuM hypervisor owned by FEN to that design to create a full platform consisting of hardware and software for future European developments within space and aeronautical applications. De-RISC brings critical features to the market that make it unique in front of the competition: (1) No US export restrictions: most existing products use US technology, thus subject to US export control. De-RISC’s IP core platform and software will not be subject to any US regulatory influence by building on RISC-V. (2) Multi-core interference mitigation concepts by BSC integrated in the RISC-V SoC and validated by TRT become a unique feature, and will provide a key advantage w.r.t. competitors by limiting drastically interference while preserving high-performance operation. (3) Portability: The proposed development will create a RISC-V HW/SW platform that can be implemented in FPGAs and application specific standard products. This provides an edge for integrators that can adapt their choice of implementation technology based on mission requirements. (4) Fault-tolerance concepts: The platform will be provided by companies with experience in the space domain and with heritage in design of fault-tolerant systems. (5) Future-proof selection for new platforms: New software products are not being ported to SPARC and PowerPC architectures. With an established vendor providing a RISC-V platform there are guarantees of continued support for the hardware platform while developments from the commercial domain for the RISC-V architecture can be leveraged over time.

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The information about "DE-RISC" are provided by the European Opendata Portal: CORDIS opendata.

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