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SAFURE

SAFety and secURity by design for interconnected mixed-critical cyber-physical systems

Total Cost €

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EC-Contrib. €

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Partnership

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Project "SAFURE" data sheet

The following table provides information about the project.

Coordinator
TECHNIKON FORSCHUNGS- UND PLANUNGSGESELLSCHAFT MBH 

Organization address
address: BURGPLATZ 3A
city: VILLACH
postcode: 9500
website: www.technikon.at

contact info
title: n.a.
name: n.a.
surname: n.a.
function: n.a.
email: n.a.
telephone: n.a.
fax: n.a.

 Coordinator Country Austria [AT]
 Project website http://www.safure.eu
 Total cost 5˙702˙631 €
 EC max contribution 5˙231˙375 € (92%)
 Programme 1. H2020-EU.2.1.1.1. (A new generation of components and systems: Engineering of advanced embedded and energy and resource efficient components and systems)
 Code Call H2020-ICT-2014-1
 Funding Scheme RIA
 Starting year 2015
 Duration (year-month-day) from 2015-02-01   to  2018-05-31

 Partnership

Take a look of project's partnership.

# participants  country  role  EC contrib. [€] 
1    TECHNIKON FORSCHUNGS- UND PLANUNGSGESELLSCHAFT MBH AT (VILLACH) coordinator 491˙300.00
2    MARELLI EUROPE SPA IT (CORBETTA) participant 622˙900.00
3    SYSGO GMBH DE (KLEIN WINTERNHEIM) participant 570˙000.00
4    THALES SA FR (COURBEVOIE) participant 552˙300.00
5    THALES SIX GTS FRANCE SAS FR (GENNEVILLIERS) participant 548˙125.00
6    SYMTAVISION GMBH DE (BRAUNSCHWEIG) participant 469˙250.00
7    ESCRYPT GMBH DE (BOCHUM) participant 456˙250.00
8    TECHNISCHE UNIVERSITAET BRAUNSCHWEIG DE (BRAUNSCHWEIG) participant 443˙500.00
9    TTTECH COMPUTERTECHNIK AG AT (WIEN) participant 431˙500.00
10    SCUOLA SUPERIORE DI STUDI UNIVERSITARI E DI PERFEZIONAMENTO S ANNA IT (PISA) participant 366˙250.00
11    BARCELONA SUPERCOMPUTING CENTER - CENTRO NACIONAL DE SUPERCOMPUTACION ES (BARCELONA) participant 280˙000.00
12    EIDGENOESSISCHE TECHNISCHE HOCHSCHULE ZUERICH CH (ZUERICH) participant 0.00

Map

 Project objective

'SAFURE targets the design of cyber-physical systems by implementing a methodology that ensures safety and security 'by construction'. This methodology is enabled by a framework developed to extend system capabilities so as to control the concurrent effects of security threats on the system behaviour. The current approach for security on safety-critical embedded systems is generally to keep subsystems separated, but this approach is now being challenged by technological evolution towards openness, increased communications and use of multi-core architectures. The objectives of SAFURE are to (1) implement a holistic approach to safety and security of embedded dependable systems, preventing and detecting potential attacks; (2) to empower designers and developers with analysis methods, development tools and execution capabilities that jointly consider security and safety; (3) to set the ground for the development of SAFURE-compliant mixed-critical embedded products. The results of SAFURE will be (1) a framework with the capability to detect, prevent and protect from security threats on safety, able to monitor from application level down to the hardware level potential attacks to system integrity from time, energy, temperature and data threats; (2) a methodology that supports the joint design of safety and security of embedded systems, assisting the designer and developers with tools and modelling languages extensions; (3) proof-of concept through 3 industrial use cases in automotive and telecommunications; (4) recommendations for extensions of standards to integrate security on safety-critical systems; (5) specifications to design and develop SAFURE-compliant products. The impact of SAFURE will help European suppliers of safety-critical embedded products to develop more cost and energy-aware solutions. To ensure this impact, a community will be created around the project. SAFURE comprises 7 industrial manufacturers, 4 leading universities and research centres and 1 SME.'

 Deliverables

List of deliverables.
Use Cases requirements Documents, reports 2020-01-23 09:33:00
Final specifications of the SAFURE Framework and Methodology Documents, reports 2020-01-23 09:33:00
Recommendations on standards evolution Documents, reports 2020-01-23 09:33:00
Data Management Plan (DMP) Open Research Data Pilot 2020-01-23 09:33:00
Final analysis of integrity algorithms Documents, reports 2020-01-23 09:33:00
Final OS & RTE prototypes Demonstrators, pilots, prototypes 2020-01-23 09:33:00
Evaluation of automotive demonstrator Documents, reports 2020-01-23 09:32:59
Architecture models and patterns for safety & security Documents, reports 2020-01-23 09:33:00
Integrity methodology Documents, reports 2020-01-23 09:33:00
Analysis of run-time and software applications on multi-core Documents, reports 2020-01-23 09:33:00
Technology watch report Documents, reports 2020-01-23 09:33:00
Evaluation of telecommunications demonstrator Documents, reports 2020-01-23 09:33:00
Internal and external IT communication infrastructure and project website Websites, patent fillings, videos etc. 2020-01-23 09:32:59
Interim analysis of integrity algorithms Documents, reports 2020-01-23 09:32:59
Alpha OS & RTE prototypes Demonstrators, pilots, prototypes 2020-01-23 09:32:59
Architecture models and patterns for safety & security (Alpha) Documents, reports 2020-01-23 09:32:59
Use Cases specifications Documents, reports 2020-01-23 09:32:59
Project quality plan Other 2020-01-23 09:32:59
Risk Assessment Plan Documents, reports 2020-01-23 09:32:59
SAFURE Framework specifications Documents, reports 2020-01-23 09:32:59

Take a look to the deliverables list in detail:  detailed list of SAFURE deliverables.

 Publications

year authors and title journal last update
List of publications.
2018 Gabriel Fernandez, Francisco J. Cazorla, Jaume Abella
Consumer Electronics Processors for Critical Real-Time Systems: a (Failed) Practical Experience
published pages: , ISSN: , DOI: 10.5281/zenodo.1199566
European Congress on Embedded Real-Time Software and Systems (ERTS2018) 2020-01-23
2015 Girbal, Sylvain ; Gracia Perez, Daniel ; Le Rhun, Jimmy ; Faugere, Madeleine ; Pagetti, Claire ; Durrieu, Guy
A complete tool-chain for an interference-free deployment of avionic applications on multi-core systems
published pages: , ISSN: , DOI: 10.5281/zenodo.128554
2015 IEEE/AIAA 34th Digital Avionics Systems Conference (DASC) Proceedings 2020-01-23
2015 Fernandez, Gabriel ; Abella, Jaume ; QuiËœnones, Eduardo ; Fossati, Luca ; Zulianello, Marco ; Vardanega, Tullio ; Cazorla, Francisco J.
Seeking Time-Composable Partitions of Tasks for COTS Multicore Processors
published pages: , ISSN: , DOI: 10.5281/zenodo.55525
2015 IEEE 18th International Symposium on Real-Time Distributed Computing (ISORC) 2020-01-23
2016 Thiele, Daniel ; Ernst, Rolf
Formal Worst-Case Timing Analysis of Ethernet TSN’s Burst-Limiting Shaper
published pages: , ISSN: , DOI: 10.5281/zenodo.55529
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE) 2020-01-23
2015 Jakovljevic, Mirko ; Plankensteiner, Markus
Deterministic Ethernet - High-speed communication with real-time guarantees
published pages: , ISSN: , DOI: 10.5281/zenodo.55518
Forum Funktionale Sicherheit 2020-01-23
2015 Jean, Xavier ; Girbal, Sylvain ; Roger, Anthony ; Megel, Thomas ; Brindejonc, Vincent
Safety considerations for WCET evaluation methods in avionic equipment
published pages: 7A4-1 - 7A4-15, ISSN: , DOI: 10.5281/zenodo.57615
2015 IEEE/AIAA 34th Digital Avionics Systems Conference (DASC) 2020-01-23
2015 Fernandez, Gabriel ; Jalle, Javier ; Abella, Jaume ; Quiñones, Eduardo ; Vardanega, Tullio ; Cazorla, Francisco J.
Resource usage templates and signatures for COTS multicore processors
published pages: , ISSN: , DOI: 10.5281/zenodo.55517
Design Automation Conference (DAC) 2020-01-23
2016 Thiele, Daniel ; Ernst, Rolf
Formal analysis based evaluation of software defined networking for time-sensitive Ethernet
published pages: , ISSN: , DOI: 10.5281/zenodo.55531
Design, Automation & Test in Europe Conference & Exhibition (DATE) 2020-01-23
2016 Daniel Thiele, Johannes Schlatow, Philip Axer, Rolf Ernst
Formal timing analysis of CAN-to-Ethernet gateway strategies in automotive networks
published pages: 88-112, ISSN: 0922-6443, DOI: 10.1007/s11241-015-9243-y
Real-Time Systems 52/1 2020-01-23
2015 Fernandez, Gabriel ; Jalle, Javier ; Abella, Jaume ; Quiñones, Eduardo ; Vardanega, Tullio ; Cazorla, Francisco J.
Increasing confidence on measurement-based contention bounds for real-time round-robin buses
published pages: , ISSN: , DOI: 10.5281/zenodo.55515
Design Automation Conference (DAC) 2020-01-23
2016 Bartolini, Davide B. ; Miedl, Philipp ; Thiele, Lothar
On the Capacity of Thermal Covert Channels in Multicores
published pages: , ISSN: , DOI: 10.5281/zenodo.57409
EuroSys\'16 2020-01-23
2015 Girbal, Sylvain ; Jean, Xavier ; Le Rhun, Jimmy ; Gracia Perez, Daniel ; Gatti, Marc
Deterministic platform software for hard real-time systems using multi-core COTS
published pages: , ISSN: , DOI: 10.5281/zenodo.57261
34th Digital Avionics System Conference (DASC), Prague, 13-17 September 2015. 2020-01-23
2015 Thiele, Daniel ; Ernst, Rolf
Formal Worst-Case Timing Analysis of Ethernet TSN’s Time-Aware and Peristaltic Shapers
published pages: , ISSN: , DOI: 10.5281/zenodo.55528
Vehicular Networking Conference (VNC), Kyoto, 16-18 December 2015. 2020-01-23
2016 Quinones, Eduardo; Fernandez, Gabriel; Jalle, Javier; Abella, Jaume; Vardanega, Tullio; Cazorla, Francisco J.
Computing Safe Contention Bounds for Multicore Resources with Round-Robin and FIFO Arbitration
published pages: , ISSN: 0018-9340, DOI: 10.5281/zenodo.165812
IEEETC 2 2020-01-23

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