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WiPLASH SIGNED

Architecting More Than Moore – Wireless Plasticity for Heterogeneous Massive Computer Architectures

Total Cost €

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EC-Contrib. €

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Partnership

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 WiPLASH project word cloud

Explore the words cloud of the WiPLASH project. It provides you a very rough idea of what is the project "WiPLASH" about.

flexibility    architecture    architectures    emergence    parallelism    wave    network    communication    principles    prototype    interconnect    heterogeneous    near    3d    computer    complemented    scalability    technological    tightly    efficiency    generality    specialized    rf    speed    units    scaling    shifted    urgent    graphene    noc    energy    plane    delay    mainly    chip    terahertz    constraints    asic    plasticity    unable    culminating    reconfigurability    antenna    integrate    mechanisms    solid    co    band    plausible    interconnects    biologically    monolithic    wiplash    computing    specialization    rigid    pioneer    enablers    memory    submillimeter    baseline    experimental    learning    miniaturized    foundations    least    transceivers    processor    introduce    functional    tunable    goals    ict    power    networks    stacking    fundamentally    integration    deep    components    diversification    interconnection    multiple    wireless    architectural    platforms    offers    10x    motivated    reconfigurable    hardware   

Project "WiPLASH" data sheet

The following table provides information about the project.

Coordinator
UNIVERSITAT POLITECNICA DE CATALUNYA 

Organization address
address: CALLE JORDI GIRONA 31
city: BARCELONA
postcode: 8034
website: www.upc.edu

contact info
title: n.a.
name: n.a.
surname: n.a.
function: n.a.
email: n.a.
telephone: n.a.
fax: n.a.

 Coordinator Country Spain [ES]
 Total cost 2˙994˙765 €
 EC max contribution 2˙994˙765 € (100%)
 Programme 1. H2020-EU.1.2.1. (FET Open)
 Code Call H2020-FETOPEN-2018-2019-2020-01
 Funding Scheme RIA
 Starting year 2019
 Duration (year-month-day) from 2019-10-01   to  2022-09-30

 Partnership

Take a look of project's partnership.

# participants  country  role  EC contrib. [€] 
1    UNIVERSITAT POLITECNICA DE CATALUNYA ES (BARCELONA) coordinator 351˙375.00
2    GESELLSCHAFT FUR ANGEWANDTE MIKRO UND OPTOELEKTRONIK MIT BESCHRANKTERHAFTUNG AMO GMBH DE (AACHEN) participant 581˙250.00
3    IBM RESEARCH GMBH CH (RUESCHLIKON) participant 507˙450.00
4    RHEINISCH-WESTFAELISCHE TECHNISCHE HOCHSCHULE AACHEN DE (AACHEN) participant 423˙437.00
5    UNIVERSITAET SIEGEN DE (SIEGEN) participant 417˙252.00
6    ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE CH (LAUSANNE) participant 385˙250.00
7    ALMA MATER STUDIORUM - UNIVERSITA DI BOLOGNA IT (BOLOGNA) participant 328˙750.00

Map

 Project objective

The main design principles in computer architecture have shifted from a monolithic scaling-driven approach towards an emergence of heterogeneous architectures that tightly co-integrate multiple specialized computing and memory units. This is motivated by the urgent need of very high parallelism and by energy constraints. This heterogeneous hardware specialization requires interconnection mechanisms that integrate the architecture. State-of-the-art approaches are 3D stacking and 2.D architectures complemented with a Network-on-Chip (NoC) to interconnect the components. However, such interconnects are fundamentally monolithic and rigid, and are unable to provide the efficiency and architectural flexibility required by current and future key ICT applications. The main challenge is to introduce diversification and specialization in heterogeneous processor architectures while ensuring their generality and scalability.

In order to achieve this, the WiPLASH project aims to pioneer an on-chip wireless communication plane able to provide architectural plasticity, reconfigurability and adaptation to the application requirements with near-ASIC efficiency but without any loss of generality. For this, the WiPLASH consortium will provide solid experimental foundations of the key enablers of on-chip wireless communication at the functional unit level as well as their technological and architectural integration. The main goals are: (i) prototype a miniaturized and tunable graphene antenna in the terahertz band, (ii) co-integrate graphene RF components with submillimeter-wave transceivers and (iii) demonstrate low-power reconfigurable wireless chip-scale networks. The culminating goal is to demonstrate that the wireless plane offers the plasticity required by future computing platforms by improving at least one key application (mainly biologically-plausible deep learning architectures) by 10X in terms of execution speed and energy-delay product over a state-of-the-art baseline.

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The information about "WIPLASH" are provided by the European Opendata Portal: CORDIS opendata.

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