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Large Scale Silicon Photonics Matrix for Low Power and Low Cost Data Centers

Total Cost €


EC-Contrib. €






Project "L3MATRIX" data sheet

The following table provides information about the project.


Organization address
postcode: 80686

contact info
title: n.a.
name: n.a.
surname: n.a.
function: n.a.
email: n.a.
telephone: n.a.
fax: n.a.

 Coordinator Country Germany [DE]
 Project website
 Total cost 3˙836˙186 €
 EC max contribution 3˙123˙966 € (81%)
 Programme 1. H2020-EU.2.1.1. (INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT))
 Code Call H2020-ICT-2015
 Funding Scheme RIA
 Starting year 2015
 Duration (year-month-day) from 2015-12-01   to  2019-05-31


Take a look of project's partnership.

# participants  country  role  EC contrib. [€] 
2    AMS AG AT (UNTERPREMSTAETTEN) participant 602˙205.00
3    DUSTPHOTONICS LTD IL (TEL AVIV - JAFFA) participant 525˙812.00
6    UNIVERSITY COLLEGE LONDON UK (LONDON) participant 323˙337.00
7    BRIGHT PHOTONICS BV NL (MAARSSEN) participant 150˙875.00
9    IBM RESEARCH GMBH CH (RUESCHLIKON) participant 0.00


 Project objective

Cloud storage and computing, big data analytics and social media are driving the need for higher bandwidth communications in data centres (DCs). Concurrently, disaggregation and virtualization trends in the DC are forcing the traffic to be between servers and storage elements in the east-west direction. These changes require massive switching capabilities from the discrete switch elements. However, the technology is rapidly reaching a limit. The result is a multi-layered DC topology with high power consumption and long latency. The L3MATRIX project provides novel technological innovations in the fields of silicon photonics (SiP) and 3D device integration. The project will develop a novel SiP matrix with a scale larger than any similar device with more than 100 modulators on a single chip and will integrate embedded laser sources with a logic chip thus breaking the limitations on the bandwidth-distance product. Use of embedded laser sources and integration with a full logic CMOS chip are innovative steps that will have a profound effect on the European market as these technologies will make a noticeable change in the power consumption, performance and cost of DCs. A novel approach will be used with embedded III-V sources on the SOI substrate which will eliminate the need to use an external light source for the modulators. L3MATRIX provides a new method of building switching elements that are both high radix and have an extended bandwidth of 25 Gb/s in single mode fibres and waveguides with low latency. The power consumption of DC networks built with these devices is 10-fold lower compared to the conventional technology. The outcome of this approach is that large networks, in the Pb/s scale can be built as a single stage, non-blocking network. The single mode nature of the SiP chip allows scaling the network to the 2000 m range required in modern DCs.


List of deliverables.
Project Final Newsletter Websites, patent fillings, videos etc. 2020-02-20 17:08:18
Final Publishable Activity Report Documents, reports 2020-02-20 17:08:18
Final Press Release Websites, patent fillings, videos etc. 2020-02-20 17:08:18
Report on L3MATRIX application scenario in the data centre Documents, reports 2020-02-20 17:08:18
Project Second Newsletter Websites, patent fillings, videos etc. 2020-02-20 17:08:18
First Project Press release Demonstrators, pilots, prototypes 2020-02-20 17:08:18
General publications, presentations and patents Documents, reports 2020-02-20 17:08:18
Project Webpage Online Websites, patent fillings, videos etc. 2020-02-20 17:08:18
Project Promotional Video Websites, patent fillings, videos etc. 2020-02-20 17:08:18
Project First Newsletter Websites, patent fillings, videos etc. 2020-02-20 17:08:17

Take a look to the deliverables list in detail:  detailed list of L3MATRIX deliverables.


year authors and title journal last update
List of publications.
2019 Terzenidis Nikolaos, Moralis-Pegios Miltiadis, Alexoudi Theonitsa, Pitris Stelios, Vyrsokinos Konstantinos, Pleros Nikolaos
Dual-layer Locality-Aware Optical Interconnection Architecture for Latency-Critical Resource Disaggregation Environments
published pages: , ISSN: , DOI:
ONDM 2019 23rd Conference on Optical Network Design and Modelling May 13-16, 2019 2020-02-20
2018 Nikos Terzenidis, Miltiadis Moralis-Pegios, George Mourgias-Alexandris, Konstantinos Vyrsokinos, Nikos Pleros
High-port low-latency optical switch architecture with optical feed-forward buffering for 256-node disaggregated data centers
published pages: 8756, ISSN: 1094-4087, DOI: 10.1364/oe.26.008756
Optics Express 26/7 2020-02-20
2019 Nikos Terzenidis, Miltiadis Moralis-Pegios, Stelios Pitris, Theoni Alexoudi and Nikos Pleros
Photonics for Disaggregated DataCenter and Computercom Architectures
published pages: , ISSN: , DOI:
4th International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems (AISTECS) 2019 co-located with the 14th HiPEAC January 21, 2019 2020-02-20
2018 Mourgias-Alexandris George, Tsakyridis Apostolos, Alexoudi Theonitsa, Vyrsokinos Konstantinos, Pleros Nikolaos
Optical Thresholding Device with a Sigmoidal Transfer Function
published pages: , ISSN: , DOI:
PSC 2018 2020-02-20
2018 G. Mourgias-Alexandris, C. Vagionas, A. Tsakyridis, P. Maniotis, N. Pleros
Optical Content Addressable Memory Matchline for 2-bit Address Look-Up at 10 Gb/s
published pages: 809-812, ISSN: 1041-1135, DOI: 10.1109/lpt.2018.2817928
IEEE Photonics Technology Letters 30/9 2020-02-20
2018 M. Moralis-Pegios, G. Mourgias-Alexandris, N. Terzenidis, M. Cherchi, M. Harjanne, T. Aalto, A. Miliou, N. Pleros, K. Vyrsokinos
On-Chip SOI Delay Line Bank for Optical Buffers and Time Slot Interchangers
published pages: 31-34, ISSN: 1041-1135, DOI: 10.1109/lpt.2017.2773146
IEEE Photonics Technology Letters 30/1 2020-02-20
2018 George Mourgias-Alexandris, Christos Vagionas, Apostolos Tsakyridis, Pavlos Maniotis, Nikos Pleros
All-optical 10Gb/s ternary-CAM cell for routing look-up table applications
published pages: 7555, ISSN: 1094-4087, DOI: 10.1364/oe.26.007555
Optics Express 26/6 2020-02-20
2019 Roberto Larrea, Ana M. Gutierrez, Amadeu Griol, Antoine Brimont, Pablo Sanchis
Fiber-to-Chip Spot-Size Converter for Coupling to Silicon Waveguides in the O-Band
published pages: 31-34, ISSN: 1041-1135, DOI: 10.1109/lpt.2018.2881334
IEEE Photonics Technology Letters 31/1 2020-02-20
2018 N. Terzenidis, M. Moralis-Pegios, G. Mourgias-Alexandris, T. Alexoudi, K. Vyrsokinos, N. Pleros
High-Port and Low-Latency Optical Switches for Disaggregated Data Centers: The Hipoλaos Switch Architecture [Invited]
published pages: B102, ISSN: 1943-0620, DOI: 10.1364/jocn.10.00b102
Journal of Optical Communications and Networking 10/7 2020-02-20
2018 M. Moralis-Pegios, N. Terzenidis, G. Mourgias-Alexandris, M. Cherchi, M. Harjanne, T. Aalto, A. Miliou, K. Vyrsokinos, N. Pleros
Multicast-Enabling Optical Switch Design Employing Si Buffering and Routing Elements
published pages: 712-715, ISSN: 1041-1135, DOI: 10.1109/lpt.2018.2813012
IEEE Photonics Technology Letters 30/8 2020-02-20
2018 N. Terzenidis, M. Moralis-Pegios, G. Mourgias-Alexandris, K. Vyrsokinos, N. Pleros
\"Multicasting in a High-Port Sub- $mu$ sec Latency Hipo $lambda$ aos Optical Packet Switch\"
published pages: 1535-1538, ISSN: 1041-1135, DOI: 10.1109/lpt.2018.2859032
IEEE Photonics Technology Letters 30/17 2020-02-20
2019 Nikos Terzenidis; Miltiadis Moralis-Pegios; George Mourgias-Alexandris; Apostolos Tsakyridis; Christos Vagionas; Konstantinos Vyrsokinos; Theoni Alexoudi; Charoula Mitsolidou; Nikos Pleros
Optics for Disaggregating DataCenters and Disintegrating Computing
published pages: , ISSN: , DOI:
ONDM 2019 23rd Conference on Optical Network Design and Modelling May 13-16, 2019 2020-02-20
2018 Miltiadis Moralis-Pegios, Nikolaos Terzenidis, George Mourgias-Alexandris, Konstantinos Vyrsokinos
Silicon Photonics towards Disaggregation of Resources in Data Centers
published pages: 83, ISSN: 2076-3417, DOI: 10.3390/app8010083
Applied Sciences 8/1 2020-02-20
2018 Marc Seifried, Gustavo Villares, Yannick Baumgartner, Herwig Hahn, Mattia Halter, Folkert Horst, Daniele Caimi, Charles Caer, Marilyne Sousa, Roger Franz Dangel, Lukas Czornomaz, Bert Jan Offrein
Monolithically Integrated CMOS-Compatible III–V on Silicon Lasers
published pages: 1-9, ISSN: 1077-260X, DOI: 10.1109/jstqe.2018.2832654
IEEE Journal of Selected Topics in Quantum Electronics 24/6 2020-02-20
2017 N. Terzenidis, M. Moralis-Pegios, C. Vagionas, S. Pitris, E. Chatzianagnostou, P. Maniotis, D. Syrivelis, L. Tassiulas, A. Miliou, N. Pleros, K. Vyrsokinos
Optically-Enabled Bloom Filter Label Forwarding Using a Silicon Photonic Switching Matrix
published pages: 4758-4765, ISSN: 0733-8724, DOI: 10.1109/jlt.2017.2760013
Journal of Lightwave Technology 35/21 2020-02-20
2019 G. Mourgias-Alexandris, A. Tsakyridis, N. Passalis, A. Tefas, K. Vyrsokinos, N. Pleros
An all-optical neuron with sigmoid activation function
published pages: 9620, ISSN: 1094-4087, DOI: 10.1364/oe.27.009620
Optics Express 27/7 2020-02-20
2017 H. Hahn, M. Seifried, G. Villares, Y. Baumgartner, M. Halter, C. Caër, D. Caimi, M. Sousa, R. Dangel, N. Meier, F. Horst, L. Czornomaz, and B. J. Offrein
Towards the integration of electro-optical hybrid III-V on Si lasers into the BEOL of a CMOS process flow
published pages: , ISSN: , DOI:
Device Research Conference, Notre Dame, IN, USA, 2017 2020-02-20
2017 M. Seifried, H. Hahn, G. Villares, F. Horst, D. Caimi, Ch. Caer, Charles Y. Baumgartner, M. Sousa, R. Dangel, L. Czornomaz, and B. J. Offrein
CMOS-Embedded Lasers for Advanced Silicon Photonic Devices
published pages: , ISSN: , DOI:
ICTON - 3rd workshop on Technology for Data Center Interconnects, Girona, Spain, 2017 2020-02-20
2016 A. Brimont
Silicon modulators and switches for Data Centers
published pages: , ISSN: , DOI:
Microphotonics Conference, Berlin, Germany, 2016 2020-02-20
2017 A. Zanzi, A. Rosa, A. Griol, P. Sanchis, J. Marti and A. Brimont
Advanced High Speed Slow Light Silicon Modulators in the O-Band for Low Power Optical Interconnects in Data Centers
published pages: , ISSN: , DOI:
14th International Conference on Group IV Photonics Conference, Berlin, Germany August 2017 2020-02-20
2017 G. Villares, M. Seifried, H. Hahn, L. Czornomaz, Ch. Caer, Y. Baumgartner, F. Horst, R. Dangel, D. Caimi, M, Sousa, N. Meier, J. Fompeyrine, and B. J. Offrein
CMOS-embedded III-V on Silicon laser sources
published pages: , ISSN: , DOI:
International Meeting on Integrated Photonics, Shanghai, China, 2017 2020-02-20
2017 Konstantinos Vyrsokinos, M. Moralis-Pegios, George Mourgias-Alexandris, N. Terzenidis and N. Pleros
Optical packet forwarding and time rearrangement based on Double Wavelength Conversion with SOA-MZI gates
published pages: , ISSN: , DOI:
ICTON 2017, July 2017, Girona, Spain 2020-02-20
2017 A. Zanzi, P.Sanchis, J.Marti and A.Brimont
Design and Optimization of a High Speed Slow-light Silicon modulator in the O-band
published pages: , ISSN: , DOI:
19th European Conference on Integrated Optics (ECIO), Eindhoven, 2017 2020-02-20
2016 Dimitris Chatzitheocharis, Konstantinos Vyrsokinos and Sotirios Ves
Investigation of Silicon Nanophotonic Single-Mode Polarization Insensitive Waveguides
published pages: , ISSN: , DOI:
XXXII Panhellenic Conference on Solid State Physics & Materials Science, September 2016, Ioannina, Greece 2020-02-20
2017 Herwig Hahn, Marilyne Sousa, Lukas Czornomaz
Low-resistive, CMOS-compatible ohmic contact schemes to moderately doped n-InP
published pages: 235102, ISSN: 0022-3727, DOI: 10.1088/1361-6463/aa6f7a
Journal of Physics D: Applied Physics 50/23 2020-02-20
2016 A. Zanzi, A.Brimont, P.Sanchis and J.Marti
Design of a High Speed Silicon Modulator Based on a Vertical pn Junction at 1.31 μm Wavelegnth
published pages: , ISSN: , DOI:
18th European Conference on Integrated Optics (ECIO), Varsaw, 2016 2020-02-20
2017 Miltiadis Moralis-Pegios, George Mourgias-Alexandris, Nikos Terzenidis, Matteo Cherchi, Mikko Harjanne, Timo Aalto, Amalia Miliou, Nikos Pleros, and Konstantinos Vyrsokinos
Optical Buffering and Time-Slot Interchanger with integrated Si-based delay lines
published pages: , ISSN: , DOI:
IEEE Summer Topical Meeting, July 2017, San Juan, Puerto Rico 2020-02-20
2017 N. Pleros
Chip-scale disaggregated computing via Silicon Photonics: can be more than replacing a link!
published pages: , ISSN: , DOI:
ECOC 2017, Workshop on Silicon Photonics 2020-02-20

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