spOt

Spin Orbit Torque memory for cache & Multicore processor applications

Coordinatore	CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE    more  Organization address address: avenue des martyrs 25 city: Grenoble postcode: 38042 contact info Titolo: Mr. Nome: Guillaume Cognome: ROCHET Email: send email Telefono: +33 4 76881005 Fax: +33 4 76881174
Nazionalità Coordinatore	France [FR]
Totale costo	4˙414˙901 €
EC contributo	3˙200˙000 €
Programma	FP7-ICT Specific Programme "Cooperation": Information and communication technologies
Code Call	FP7-ICT-2011-8
Funding Scheme	CP
Anno di inizio	2012
Periodo (anno-mese-giorno)	2012-10-01   -   2015-09-30

 Partecipanti

#	participant	country	role	EC contrib. [€]
1	CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE  Organization address address: avenue des martyrs 25 city: Grenoble postcode: 38042 contact info Titolo: Mr. Nome: Guillaume Cognome: ROCHET Email: send email Telefono: +33 4 76881005 Fax: +33 4 76881174	FR (Grenoble)	coordinator	0.00
2	COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES  Organization address address: RUE LEBLANC 25 city: PARIS 15 postcode: 75015 contact info Titolo: Ms. Nome: Marie-Claire Cognome: CYRILLE Email: send email Telefono: +33 4 38781791	FR (PARIS 15)	participant	0.00
3	EIDGENOESSISCHE TECHNISCHE HOCHSCHULE ZURICH  Organization address address: Raemistrasse 101 city: ZUERICH postcode: 8092 contact info Titolo: Prof. Nome: Pietro Cognome: Gambardella Email: send email Telefono: +41 44 633 07 56	CH (ZUERICH)	participant	0.00
4	INSTITUT POLYTECHNIQUE DE GRENOBLE  Organization address address: AVENUE FELIX VIALLET 46 city: GRENOBLE CEDEX 1 postcode: 38031 contact info Titolo: Ms. Nome: Clémentine Cognome: GLEIZAL Email: send email Telefono: +33 4 76 57 50 38 Fax: +33 4 56 52 89 00	FR (GRENOBLE CEDEX 1)	participant	0.00
5	Karlsruher Institut fuer Technologie  Organization address address: Kaiserstrasse 12 city: Karlsruhe postcode: 76131 contact info Titolo: Prof. Nome: Mehdi Cognome: Tahoori Email: send email Telefono: +49 721 608 47778 Fax: +49 721 608 25403	DE (Karlsruhe)	participant	0.00
6	NATIONAL CENTER FOR SCIENTIFIC RESEARCH "DEMOKRITOS"  Organization address address: Patriarchou Gregoriou Str. city: AGHIA PARASKEVI postcode: 15310 contact info Titolo: Mr. Nome: Euripides Cognome: Papadopoulos Email: send email Telefono: +30 210 6503037 Fax: +30 210 6522623	EL (AGHIA PARASKEVI)	participant	0.00
7	Singulus Technologies AG  Organization address address: Hanauer Landstrasse 103 city: KAHL AM MAIN postcode: 63796 contact info Titolo: Mr. Nome: Berthold Cognome: Ocker Email: send email Telefono: +49 6188 440 416 Fax: +49 6188 440 480	DE (KAHL AM MAIN)	participant	0.00
8	TOPLINK INNOVATION  Organization address city: La Seyne sur Mer postcode: 83500 contact info Titolo: Dr. Nome: Alexandre Cognome: LORENZI Email: send email Telefono: +33 4 94 10 72 57 Fax: +33 4 94 63 61 99	FR (La Seyne sur Mer)	participant	0.00

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 Obiettivo del progetto (Objective)

The microelectronics industry will face major challenges related to power dissipation and energy consumption in the next years. Both static and dynamic consumption will soon start to limit microprocessor performance growth. The goal of the spOt project is to modify the memory hierarchy by the integration of non-volatility (NV) as a new feature of memory cache, which would immediately minimize static power as well as paving the way towards normally-off/instant-on computing.nTo accomplish this aggressive goal, limitations of present NV memories in terms of speed and endurance must be overcome and new architectures taking full benefit of these new functionalities must be developed. The consortium will base its research on a recent discovery achieved jointly by SPINTEC and ICN, called 'Spin Orbit Torque' (SOT). This disruptive technology, which can be viewed as the ultimate evolution of Spin Transfer Torque, offers the same non-volatility and compliance with technological nodes below 22nm, with the addition of lower power consumption, cache-compatible high speed, and truly infinite endurance.nTo demonstrate its viability for cache, a number of identified technology roadblocks are addressed by the spOt project through its 5 work-packages and 4 intermediate goals: i) the realization of a fast write, low power, high read signal single memory cell ii) the development of a single cell architecture (standard cell) with minimal footprint iii) A stand-alone memory test chip with full functionality iv) The full chip simulation of a low-power/normally-off multicore processor.nThe final objective of the project is twofold: The fabrication of a SOT memory test chip, which would be benchmarked against existing and forecasted solutions in order to demonstrate the integrability and manufacturability of this new technology; The design and full chip simulation of a novel multicore processor integrating embedded SOT memory, in order to demonstrate the systemability of such approach.