REALITY

Reliable and Variability tolerant System-on-a-chip Design in More-Moore Technologies

 Coordinatore INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW 

 Organization address address: KAPELDREEF 75
city: LEUVEN
postcode: 3001

contact info
Titolo: Mrs.
Nome: Christine
Cognome: Van Houtven
Email: send email
Telefono: +3216281 613
Fax: +3216281 812

 Nazionalità Coordinatore Belgium [BE]
 Sito del progetto http://www.imec.be/reality/index.htm
 Totale costo 4˙447˙211 €
 EC contributo 2˙899˙883 €
 Programma FP7-ICT
Specific Programme "Cooperation": Information and communication technologies
 Code Call FP7-ICT-2007-1
 Funding Scheme CP
 Anno di inizio 2008
 Periodo (anno-mese-giorno) 2008-01-01   -   2010-08-31

 Partecipanti

# participant  country  role  EC contrib. [€] 
1    INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM VZW

 Organization address address: KAPELDREEF 75
city: LEUVEN
postcode: 3001

contact info
Titolo: Mrs.
Nome: Christine
Cognome: Van Houtven
Email: send email
Telefono: +3216281 613
Fax: +3216281 812

BE (LEUVEN) coordinator 0.00
2    ALMA MATER STUDIORUM-UNIVERSITA DI BOLOGNA

 Organization address address: Via Zamboni
city: BOLOGNA
postcode: 40126

contact info
Titolo: Ms.
Nome: Eleonora
Cognome: Medeot
Email: send email
Telefono: -2093029
Fax: -2093029

IT (BOLOGNA) participant 0.00
3    ARM LIMITED

 Organization address address: 110 FULBOURN ROAD
city: CAMBRIDGE
postcode: CB1 9NJ

contact info
Titolo: Mr.
Nome: Stephen
Cognome: Doel
Email: send email
Telefono: +44 1223 400898
Fax: +44 1223 400410

UK (CAMBRIDGE) participant 0.00
4    KATHOLIEKE UNIVERSITEIT LEUVEN

 Organization address address: Oude Markt
city: LEUVEN
postcode: 3000

contact info
Titolo: Ir
Nome: Maria
Cognome: Vereeken
Email: send email
Telefono: -326488
Fax: -326499

BE (LEUVEN) participant 0.00
5    STMICROELECTRONICS SRL

 Organization address address: VIA C.OLIVETTI
city: AGRATE BRIANZA
postcode: 20041

contact info
Titolo: Dr
Nome: Maria Grazia
Cognome: Podesta
Email: send email
Telefono: -6037255
Fax: -6035910

IT (AGRATE BRIANZA) participant 0.00
6    UNIVERSITY OF GLASGOW

 Organization address address: University Avenue
city: GLASGOW
postcode: G12 8QQ

contact info
Titolo: Mr.
Nome: Joe
Cognome: Galloway
Email: send email
Telefono: -3303981
Fax: -3305708

UK (GLASGOW) participant 0.00

Mappa


 Word cloud

Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.

energy    reliability    fault    technologies    variability    nthe    dynamic    unreliable    soc    performance    time    real    impact       static    rates    nm    techniques    efficient   

 Obiettivo del progetto (Objective)

As miniaturization of the CMOS technology advances designers will have to deal with increased variability and changing performance of devices. Intrinsic variability of devices which begins to be visible in 65nm devices already will become much more significant in smaller technologies. Soon it will not be possible to design systems using current methods and techniques.nScaling beyond the 32 nm technology node brings a number of problems whose impact on design has not been evaluated yet. Random intra-die process variability, reliability degradation mechanisms and their combined impact on the system level parametric quality metrics are becoming prominent issues.nnDealing with these new challenges will require an adaptation of the current design process: a combination of design time and runtime techniques and methods will be needed to guarantee the correct functioning of Systems on Chip (SoC) over the product's lifetime, despite the fabrication in unreliable nano-scale technologies.nThe objective of this project is to develop design techniques and methods for real-time guaranteed, energy-efficient, robust and self-adaptive SoCs.nThe technological challenges to be tackled are:n(a) Increased static variability and static fault rates of devices and interconnects;n(b) Increased time-dependent dynamic variability and dynamic fault rates.n(c) Build reliable systems out of unreliable technology while maintaining design productivity;n(d) Deploy design techniques that allow technology scalable energy efficient SoC systems while guaranteeing real-time performance constraints.nnIn order to tackle these challenges we focus our effort along two main axes:n(a) Analysis of the system in terms of performance, power and reliability of manufactured instances across a wide spectrum of operating conditions.n(b) Solution techniques to mitigate impact of reliability issues of integrated circuits, at component, circuit, and architecture and system design.

Altri progetti dello stesso programma (FP7-ICT)

Dicta-Sign (2009)

Sign Language Recognition, Generation and Modelling n with application in Deaf Communication

Read More  

VAALID (2008)

Accessibility and usability validation framework for AAL interaction design process

Read More  

DOTSENSE (2008)

Group III-nitride quantum dots as optical transducers for chemical sensors

Read More