| Coordinatore | ISTITUTO NAZIONALE DI FISICA NUCLEARE
Organization address
address: piazzale Aldo Moro 2 contact info |
| Nazionalità Coordinatore | Italy [IT] |
| Totale costo | 6˙026˙817 € |
| EC contributo | 4˙599˙080 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2009-4 |
| Funding Scheme | CP |
| Anno di inizio | 2010 |
| Periodo (anno-mese-giorno) | 2010-01-01 - 2014-09-30 |
| # | ||||
|---|---|---|---|---|
| 1 |
ISTITUTO NAZIONALE DI FISICA NUCLEARE
Organization address
address: piazzale Aldo Moro 2 contact info |
IT (Rome) | coordinator | 0.00 |
| 2 |
EIDGENOESSISCHE TECHNISCHE HOCHSCHULE ZURICH
Organization address
address: Raemistrasse contact info |
CH (ZUERICH) | participant | 0.00 |
| 3 |
RHEINISCH-WESTFAELISCHE TECHNISCHE HOCHSCHULE AACHEN
Organization address
address: Templergraben contact info |
DE (AACHEN) | participant | 0.00 |
| 4 |
Target Compiler Technologies NV
Organization address
address: Technologielaan contact info |
BE (LEUVEN) | participant | 0.00 |
| 5 |
UNIVERSITE JOSEPH FOURIER GRENOBLE 1
Organization address
address: Avenue Centrale, Domaine Universitaire contact info |
FR (GRENOBLE) | participant | 0.00 |
Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.
EURETILE investigates and implements brain-inspired and fault-tolerant foundational innovations to the system architecture of massively parallel tiled computer architectures and the corresponding programming paradigm. The execution targets are a many-tile HW platform, and a many-tile simulator. A set of SW process - HW tile mapping candidates is generated by the holistic SW tool-chain using a combination of analytic and bio-inspired methods. The Hardware dependent Software is then generated, providing OS services with maximum efficiency/minimal overhead. The many-tile simulator collects profiling data, closing the loop of the SW tool chain. Fine-grain parallelism inside processes is exploited by optimized intra-tile compilation techniques, but the project focus is above the level of the elementary tile. The elementary HW tile is a multi-processor, which includes a fault tolerant Distributed Network Processor (for inter-tile communication) and ASIP accelerators. Furthermore, EURETILE investigates and implements the innovations for equipping the elementary HW tile with high-bandwidth, low-latency brain-like inter-tile communication emulating 3 levels of connection hierarchy, namely neural columns, cortical areas and cortex, and develops a dedicated cortical simulation benchmark: DPSNN-STDP (Distributed Polychronous Spiking Neural Net with synaptic Spiking Time Dependent Plasticity). EURETILE leverages on the multi-tile HW paradigm and SW tool-chain developed by the FET-ACA SHAPES Integrated Project (2006-2009).
Novel Design Principles and Technologies for a New Generation of High Dexterity Soft-bodied Robots Inspired by the Morphology and Behaviour of the Octopus
Read MoreDeveloping Versatile and Robust Perception using Sonar Systems that Integrate Active Sensing, Morphology and Behaviour
Read MoreA SOCIAL COLLABORATIVE WORKING SPACE SEMANTICALLY INTERLINKING BIOMEDICAL RESEARCHERS, KNOWLEDGE AND DATA FOR THE DESIGN AND EXECUTION OF IN-SILICO MODELS AND EXPERIMENTS IN CANCER CHEMOPREVENTION
Read More