STEEPER
Steep subthreshold slope switchesnfor energy efficient electronics
| Coordinatore | ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE
Organization address
address: ELB335, Station 11 contact info |
| Nazionalità Coordinatore | Switzerland [CH] |
| Totale costo | 6˙111˙900 € |
| EC contributo | 4˙099˙999 € |
| Programma | FP7-ICT
Specific Programme "Cooperation": Information and communication technologies |
| Code Call | FP7-ICT-2009-5 |
| Funding Scheme | CP |
| Anno di inizio | 2010 |
| Periodo (anno-mese-giorno) | 2010-06-01 - 2013-11-30 |
Partecipanti
| # | ||||
|---|---|---|---|---|
| 1 |
ECOLE POLYTECHNIQUE FEDERALE DE LAUSANNE
Organization address
address: ELB335, Station 11 contact info |
CH (Lausanne) | coordinator | 0.00 |
| 2 |
ALMA MATER STUDIORUM-UNIVERSITA DI BOLOGNA
Organization address
address: Via Zamboni contact info |
IT (BOLOGNA) | participant | 0.00 |
| 3 |
COMMISSARIAT A L ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
Organization address
address: RUE LEBLANC contact info |
FR (PARIS 15) | participant | 0.00 |
| 4 |
CONSORZIO NAZIONALE INTERUNIVERSITARIO PER LA NANOELETTRONICA
Organization address
address: VIA TOFFANO contact info |
IT (BOLOGNA) | participant | 0.00 |
| 5 |
FORSCHUNGSZENTRUM JUELICH GMBH
Organization address
address: WILHELM JOHNEN STRASSE contact info |
DE (JUELICH) | participant | 0.00 |
| 6 |
GLOBALFOUNDRIES Dresden Module One LLC & Co. KG
Organization address
address: Wilschdorfer Landstrasse contact info |
DE (Dresden) | participant | 0.00 |
| 7 |
IBM RESEARCH GMBH
Organization address
address: SAEUMERSTRASSE contact info |
CH (RUESCHLIKON) | participant | 0.00 |
| 8 |
INTEL MOBILE COMMUNICATIONS GMBH
Organization address
address: AM CAMPEON contact info |
DE (NEUBIBERG) | participant | 0.00 |
| 9 |
RHEINISCH-WESTFAELISCHE TECHNISCHE HOCHSCHULE AACHEN
Organization address
address: Templergraben contact info |
DE (AACHEN) | participant | 0.00 |
| 10 |
SCIPROM SARL
Organization address
address: RUE DU CENTRE contact info |
CH (Saint-Sulpice) | participant | 0.00 |
| 11 |
UNIVERSITA DEGLI STUDI DI UDINE
Organization address
address: VIA PALLADIO contact info |
IT (UDINE) | participant | 0.00 |
| 12 |
UNIVERSITA DI PISA
Organization address
address: Lungarno Pacinotti contact info |
IT (PISA) | participant | 0.00 |
Mappa
Word cloud
Esplora la "nuvola delle parole (Word Cloud) per avere un'idea di massima del progetto.
Obiettivo del progetto (Objective)
STEEPER addresses the development of Beyond CMOS energy-efficient steep subthreshold slope transistors based on quantum mechanical band-to-band tunnelling (tunnel FETs), with the aim of reducing the operation voltage of nanoelectronic circuits to sub-0.5V, and their power consumption by one order of magnitude.nSTEEPER focuses on two technology tracks, united by same device principle, shared performance boosters, and compatibility with silicon CMOS. These are (i) Ultra-Thin-Body Silicon-On-Insulator technology for planar, tri-gate and nanowire tunnel FETs featuring ultra-low standby power and smartly exploiting additive boosters: high-k dielectrics, SiGe source, strain, and improved electrostatic design, and (ii) a III-V nanowire platform on silicon, as unique material to control staggered or broken bandgap boosters and devise a high performance (high-Ion, steep slope) implementation of tunnel FETs. Platform (i) will enable a hybrid platform combining high performance (HP) CMOS and low standby power (LSTP), low voltage tunnel FETs, supporting energy efficient hybrid CMOS/Tunnel-FET digital and analog/RF circuit design. In line with ITRS, STEEPER will evaluate in platform (ii) the physical and practical limits of boosting the performance of tunnel FETs with III-V nanowires on silicon, and resulting advantages for HP digital circuits.nThe development of the two technology platforms are interactive and collaborative in terms of performance boosters, and will benefit from simulation and modelling support by the academic partners, and from investigation of the potentially critical variability and sensitivity of tunnel FETs. Industrial benchmarking is proposed at device and circuit levels by the key involved industries, and the figures of merit of hybrid CMOS/tunnel FET digital and analog circuit design will be investigated.nThe project targets energy efficient nanoelectronic technology for high volume markets covering digital, analog/RF and mixed mode applications.