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Wave-Locked Loop

Wave-Locked Loop for Frequency Synthesis (WLL)

Total Cost €


EC-Contrib. €






 Wave-Locked Loop project word cloud

Explore the words cloud of the Wave-Locked Loop project. It provides you a very rough idea of what is the project "Wave-Locked Loop" about.

data    lc    difficult    oscillator    break    discrete    measured    analog    tapeout    digitally    finer    tradeoff    limited    time    error    shows    detection    model    utilizing    integration    give    point    band    degree    2005    filtering    reference    samples    clocks    performance    verify    dco    variations    flicker    area    input    lock    output    waveform    innovative    robustness    converter    oversample    consuming    adpll    digitize    clock    wave    building    filter    compare    preliminary    generation    fine    digital    dynamic    domain    ring    power    designing    instead    blocks    10    sampling    small    distortion    sized    unfortunately    tdc    pvt    cmos    conventional    pll    reconstruct    reconfigured    corner    synthesizer    possibility    noise    amplitude    longer    oversampling    locked    delay    frequency    bandwidth    single    fast    precise    fellowship    loop    bulky    wll    mm    resolution    occupies   

Project "Wave-Locked Loop" data sheet

The following table provides information about the project.


Organization address
address: BELFIELD
city: DUBLIN
postcode: 4

contact info
title: n.a.
name: n.a.
surname: n.a.
function: n.a.
email: n.a.
telephone: n.a.
fax: n.a.

 Coordinator Country Ireland [IE]
 Project website
 Total cost 175˙866 €
 EC max contribution 175˙866 € (100%)
 Programme 1. H2020-EU.1.3.2. (Nurturing excellence by means of cross-border and cross-sector mobility)
 Code Call H2020-MSCA-IF-2016
 Funding Scheme MSCA-IF-EF-ST
 Starting year 2017
 Duration (year-month-day) from 2017-04-01   to  2019-03-31


Take a look of project's partnership.

# participants  country  role  EC contrib. [€] 


 Project objective

Conventional analog Phase-Locked Loop (PLL) occupies large area and is difficult to be reconfigured due to a bulky loop filter. In 2005, phase-domain all-digital phase-locked-loop (ADPLL) was proposed. It measured output phase of digitally controlled oscillator (DCO) using a time-to-digital converter (TDC). Unfortunately, designing fine-resolution TDC and wide dynamic range is power-consuming. In this project, instead of utilizing single sampling point per reference clock, we propose to oversample and digitize oscillator oscillator waveform which will produce enough digital samples to reconstruct, now in digital domain, the waveform and compare against a model waveform which will give precise frequency/phase and amplitude information. Thus, it is called, wave-locked loop (WLL) that will result in low-in-band phase noise, fast lock time, and wide-loop bandwidth that is no longer limited by reference clock. Preliminary data shows finer than 1-degree phase resolution even with 10% delay error in sampling clocks, and distortion from input waveform. This shows possibility to break the tradeoff in traditional TDC and improve robustness over PVT variations. Moreover, the design of building blocks which includes low-flicker-noise mm-wave LC Digitally-Controlled Oscillator (DCO) and small-sized ring oscillator with phase noise filtering will be investigated. Thus, this fellowship program studies an innovative frequency synthesizer and clock generation systems using wave-locked loop, which includes the study of oversampling of oscillator waveform for fine phase detection, the study of phase-noise reduction in ring oscillator using discrete-time filtering, the study of mm-wave oscillator with flicker noise corner reduction, and system integration for wave-locked loop system. The proposed synthesizer will be tapeout using advanced CMOS technology and will be measured to verify their performance.


year authors and title journal last update
List of publications.
2019 J. Du, Y. Hu, T. Siriburanon, and R. B. Staszewski
A 0.3 V, 35% tuning-range, 60 kHz 1/f3-corner digitally controlled oscillator with vertically integrated switched capacitor banks achieving FoMT of -199 dB in 28-nm CMOS
published pages: , ISSN: , DOI:
Proc. of IEEE Custom Integrated Circuits Conf. (CICC) 2020-01-27
2019 Z. Gao, Y. Hu, T. Siriburanon, and R. B. Staszewski,
28GHz quadrature frequency generation exploiting injection locked harmonic extractors for 5G communications
published pages: , ISSN: , DOI:
Proc. of 17th IEEE International NEWCAS Conf. (NEWCAS) 2020-01-27
2019 Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
Intuitive Understanding of Flicker Noise Reduction via Narrowing of Conduction Angle in Voltage-Biased Oscillators
published pages: 1-1, ISSN: 1549-7747, DOI: 10.1109/tcsii.2019.2896483
IEEE Transactions on Circuits and Systems II: Express Briefs 2020-01-27
2018 Naser Pourmousavian, Feng-Wei Kuo, Teerachot Siriburanon, Masoud Babaie, Robert Bogdan Staszewski
A 0.5-V 1.6-mW 2.4-GHz Fractional-N All-Digital PLL for Bluetooth LE With PVT-Insensitive TDC Using Switched-Capacitor Doubler in 28-nm CMOS
published pages: 2572-2583, ISSN: 0018-9200, DOI: 10.1109/jssc.2018.2843337
IEEE Journal of Solid-State Circuits 53/9 2020-01-27
2018 Yizhe Hu, Teerachot Siriburanon, Robert Bogdan Staszewski
A Low-Flicker-Noise 30-GHz Class-F 23 Oscillator in 28-nm CMOS Using Implicit Resonance and Explicit Common-Mode Return Path
published pages: 1977-1987, ISSN: 0018-9200, DOI: 10.1109/jssc.2018.2818681
IEEE Journal of Solid-State Circuits 53/7 2020-01-27

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The information about "WAVE-LOCKED LOOP" are provided by the European Opendata Portal: CORDIS opendata.

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