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MNEMOSENE SIGNED

Computation-in-memory architecture based on resistive devices

Total Cost €

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EC-Contrib. €

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Partnership

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Project "MNEMOSENE" data sheet

The following table provides information about the project.

Coordinator
TECHNISCHE UNIVERSITEIT DELFT 

Organization address
address: STEVINWEG 1
city: DELFT
postcode: 2628 CN
website: www.tudelft.nl

contact info
title: n.a.
name: n.a.
surname: n.a.
function: n.a.
email: n.a.
telephone: n.a.
fax: n.a.

 Coordinator Country Netherlands [NL]
 Project website http://www.mnemosene.eu
 Total cost 3˙998˙120 €
 EC max contribution 3˙998˙120 € (100%)
 Programme 1. H2020-EU.2.1.1. (INDUSTRIAL LEADERSHIP - Leadership in enabling and industrial technologies - Information and Communication Technologies (ICT))
 Code Call H2020-ICT-2017-1
 Funding Scheme RIA
 Starting year 2018
 Duration (year-month-day) from 2018-01-01   to  2020-12-31

 Partnership

Take a look of project's partnership.

# participants  country  role  EC contrib. [€] 
1    TECHNISCHE UNIVERSITEIT DELFT NL (DELFT) coordinator 763˙636.00
2    TECHNISCHE UNIVERSITEIT EINDHOVEN NL (EINDHOVEN) participant 645˙962.00
3    ARM LIMITED UK (CAMBRIDGE) participant 523˙183.00
4    STICHTING IMEC NEDERLAND NL (EINDHOVEN) participant 450˙750.00
5    EIDGENOESSISCHE TECHNISCHE HOCHSCHULE ZUERICH CH (ZUERICH) participant 423˙750.00
6    IBM RESEARCH GMBH CH (RUESCHLIKON) participant 416˙750.00
7    RHEINISCH-WESTFAELISCHE TECHNISCHE HOCHSCHULE AACHEN DE (AACHEN) participant 334˙250.00
8    INSTITUT NATIONAL DE RECHERCHE ENINFORMATIQUE ET AUTOMATIQUE FR (LE CHESNAY CEDEX) participant 239˙837.00
9    INTELLIGENTSIA CONSULTANTS SARL LU (BERTRANGE) participant 200˙000.00

Map

 Project objective

'The MNEMOSENE project aims at demonstrating a new computation-in-memory (CIM) based on resistive devices together with its required programming flow and interface. To develop the new architecture, the following scientific and technical objectives will be targeted:

• Objective 1: Develop new algorithmic solutions for targeted applications for CIM architecture. • Objective 2: Develop and design new mapping methods integrated in a framework for efficient compilation of the new algorithms into CIM macro-level operations; each of these is mapped to a group of CIM tiles. • Objective 3: Develop a macro-architecture based on the integration of group of CIM tiles, including the overall scheduling of the macro-level operation, data accesses, inter-tile communication, the partitioning of the crossbar, etc. • Objective 4: Develop and demonstrate the micro-architecture level of CIM tiles and their models, including primitive logic and arithmetic operators, the mapping of such operators on the crossbar, different circuit choices and the associated design trade-offs, etc. • Objective 5: Design a simulator (based on calibrated models of memristor devices & building blocks) and FPGA emulator for the new architecture (CIM device combined with conventional CPU) in order demonstrate its superiority. Demonstrate the concept of CIM by performing measurements on fabricated crossbar mounted on a PCB board.

A demonstrator will be produced and tested to show that the storage and processing can be integrated in the same physical location to improve energy efficiency and also to show that the proposed accelerator is able to achieve the following measurable targets (as compared with a general purpose multi-core platform) for the considered applications:

• Improve the energy-delay product by factor of 100X to 1000X • Improve the computational efficiency (#operations / total-energy) by factor of 10X to 100X • Improve the performance density (# operations per area) by factor of 10X to 100X'

 Deliverables

List of deliverables.
Initial models of memristive device Documents, reports 2020-02-11 12:23:11
First version backend compiler for micro-instructions Documents, reports 2020-02-11 12:23:11
Promotional material Websites, patent fillings, videos etc. 2020-02-11 12:23:11
Project website Websites, patent fillings, videos etc. 2020-02-11 12:23:11
Initial communication protocols and infrastructure Documents, reports 2020-02-11 12:23:11
First version programming interface at the micro- and macro-levels Documents, reports 2020-02-11 12:23:11
Initial memristor crossbar based logic/ arithmetic and memory designs and models Documents, reports 2020-02-11 12:23:11
Initial CIM microarchitecture Documents, reports 2020-02-11 12:23:11
First report on new algorithmic solutions Documents, reports 2020-02-11 12:23:11
Report on targeted applications, their specifications, requirements Documents, reports 2020-02-11 12:23:11
Initial macro CIM architecture and CIM-ISA Documents, reports 2020-02-11 12:23:11

Take a look to the deliverables list in detail:  detailed list of MNEMOSENE deliverables.

 Publications

year authors and title journal last update
List of publications.
2020 Hersche, Michael; id_orcid0000-0003-3065-7639; Sangalli, Sara; Benini, Luca; id_orcid0000-0001-8068-3806; Rahimi, Abbas; id_orcid0000-0003-3141-4970
Evolvable Hyperdimensional Computing: Unsupervised Regeneration of Associative Memory to Recover Faulty Components
published pages: , ISSN: , DOI: 10.3929/ethz-b-000387115
2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2020) 2 2020-04-24
2020 Hersche, Michael; id_orcid0000-0003-3065-7639; Rupp, Philipp; Benini, Luca; id_orcid0000-0001-8068-3806; Rahimi, Abbas; id_orcid0000-0003-3141-4970
Compressing Subject-specific Brain–Computer Interface Models into One Model by Superposition in Hyperdimensional Space
published pages: , ISSN: , DOI: 10.3929/ethz-b-000387117
Design, Automation and Test in Europe (DATE 2020) 1 2020-04-24
2020 Hersche, Michael; id_orcid0000-0003-3065-7639; Benini, Luca; id_orcid0000-0001-8068-3806; Rahimi, Abbas; id_orcid0000-0003-3141-4970
Binary Models for Motor-Imagery Brain–Computer Interfaces: Sparse Random Projection and Binarized SVM
published pages: , ISSN: , DOI: 10.3929/ethz-b-000387116
2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS 2020) 1 2020-04-24
2019 Jintao Yu, Hoang Anh Du Nguyen, Muath Abu Lebdeh, Mottaqiallah Taouil, Said Hamdioui
Enhanced Scouting Logic: A Robust Memristive Logic Design Scheme
published pages: , ISSN: , DOI:
2020-04-04
2018 Nicolas Vasilache, Oleksandr Zinenko, Theodoros Theodoridis, Priya Goyal, Zachary DeVito, William S. Moses, Sven Verdoolaege, Andrew Adams, Albert Cohen
Tensor Comprehensions: Framework-Agnostic High-Performance Machine Learning Abstractions
published pages: , ISSN: , DOI:
Computing Research Repository (CoRR) 2020-04-04
2019 Fernando García-Redondo, Shidhartha Das, Glen Rosendale
Training DNN IoT Applications for Deployment On Analog NVM Crossbars
published pages: , ISSN: , DOI:
2020-04-04
2019 Jie Zhao, Albert Cohen
Flextended Tiles
published pages: 1-25, ISSN: 1544-3566, DOI: 10.1145/3369382
ACM Transactions on Architecture and Code Optimization 16/4 2020-04-04
2019 Nicolas Vasilache, Oleksandr Zinenko, Theodoros Theodoridis, Priya Goyal, Zachary Devito, William S. Moses, Sven Verdoolaege, Andrew Adams, Albert Cohen
The Next 700 Accelerated Layers
published pages: 1-26, ISSN: 1544-3566, DOI: 10.1145/3355606
ACM Transactions on Architecture and Code Optimization 16/4 2020-04-04
2019 F. Cüppers, S. Menzel, C. Bengel, A. Hardtdegen, M. von Witzleben, U. Böttger, R. Waser, S. Hoffmann-Eifert
Exploiting the switching dynamics of HfO 2 -based ReRAM devices for reliable analog memristive behavior
published pages: 91105, ISSN: 2166-532X, DOI: 10.1063/1.5108654
APL Materials 7/9 2020-04-04
2019 A. Siemon, S. Ferch, A. Heittmann, R. Waser, D. J. Wouters, S. Menzel
Analyses of a 1-layer neuromorphic network using memristive devices with non-continuous resistance levels
published pages: 91110, ISSN: 2166-532X, DOI: 10.1063/1.5108658
APL Materials 7/9 2020-04-04
2020 Andi Drebes, Lorenzo Chelini, Oleksandr Zinenko, Albert Cohen, Henk Corporaal, Tobias Grosser, Kanishkan Vadivel, Nicolas Vasilache
TC-CIM: Empowering Tensor Comprehensions for Computation in Memory
published pages: , ISSN: , DOI:
2020-04-04
2019 Schmuck, Manuel; Benini, Luca; Rahimi, Abbas
Hardware Optimizations of Dense Binary Hyperdimensional Computing: Rematerialization of Hypervectors, Binarized Bundling, and Combinational Associative Memory
published pages: , ISSN: 1550-4832, DOI: 10.3929/ethz-b-000338354
ACM Journal on Emerging Technologies in Computing Systems 4 2020-02-11
2019 Simone Benatti, Fabio Montagna, Victor Kartsch, Abbas Rahimi, Davide Rossi, Luca Benini
Online Learning and Classification of EMG-Based Gestures on a Parallel Ultra-Low Power Platform Using Hyperdimensional Computing
published pages: 516-528, ISSN: 1932-4545, DOI: 10.1109/tbcas.2019.2914476
IEEE Transactions on Biomedical Circuits and Systems 13/3 2020-02-11
2019 Burrello, Alessio; Cavigelli, Lukas; id_orcid0000-0003-1767-7715; Schindler, Kaspar; Benini, Luca; id_orcid0000-0001-8068-3806; Rahimi, Abbas; id_orcid0000-0003-3141-4970
Laelaps: An Energy-Efficient Seizure Detection Algorithm from Long-term Human iEEG Recordings without False Alarms
published pages: , ISSN: , DOI: 10.3929/ethz-b-000307983
Proceedings of the 2019 Design, Automation & Test in Europe Conference & Exhibition (DATE) 4 2020-02-11
2018 Manuel Le Gallo, Abu Sebastian, Giovanni Cherubini, Heiner Giefers, Evangelos Eleftheriou
Compressed Sensing With Approximate Message Passing Using In-Memory Computing
published pages: 1-9, ISSN: 0018-9383, DOI: 10.1109/TED.2018.2865352
IEEE Transactions on Electron Devices 2020-02-11
2018 S. R. Nandakumar, Manuel Le Gallo, Irem Boybat, Bipin Rajendran, Abu Sebastian, Evangelos Eleftheriou
A phase-change memory model for neuromorphic computing
published pages: 152135, ISSN: 0021-8979, DOI: 10.1063/1.5042408
Journal of Applied Physics 124/15 2020-02-11
2019 Alessio Burrello, Kaspar Anton Schindler, Luca Benini, Abbas Rahimi
Hyperdimensional Computing with Local Binary Patterns: One-shot Learning for Seizure Onset Detection and Identification of Ictogenic Brain Regions from Short-time iEEG Recordings
published pages: 1-1, ISSN: 0018-9294, DOI: 10.1109/tbme.2019.2919137
IEEE Transactions on Biomedical Engineering 2020-02-11

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