Hastlayer SIGNED

Project "Hastlayer" data sheet

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 Project objective

High-level synthesis (HLS) is increasingly popular for the design of high-performance and energy-efficient heterogeneous systems, shortening time-to-market and addressing today’s system complexity. HLS allows designers to work at a higher-level of abstraction by using a software program to specify the hardware functionality. Additionally, HLS is particularly interesting for designing field-programmable gate array circuits (FPGA), where hardware implementations can be easily refined and replaced in the target device. Recent years have seen much activity in the HLS research community, with a plethora of HLS tool offerings, from both industry and academia, but none of these solutions are widespread for industrial use. FPGA Programming requires certain skills, specific knowledge and specialised hardware. Gathering these are expensive and due to this limitation can only be achieved by a small fraction of software developers, which makes access to FPGA equally limited. With our solution we aim to give access to those software engineers who lack this specific knowledge. Hastlayer a provides an HLS service consisting of multiple tools that allows desktop, web and mobile software developers to increase the performance of their computationally intensive and resource demanding applications by executing critical parts of their software on a specialised hardware architecture remotely or locally (FPGA) without having the in-depth knowledge of such platforms. This solution results in lower development cost when it comes to optimisation, cheaper hardware when it comes to speeding up a slow program but most importantly makes continuous development exceptionally fast. Before we can turn Hastlayer into a product we need to carry out a feasibility study in order to define use cases tackle security issues and develop the most suitable business mode to maximize market penetration.