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RESCUE SIGNED

Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems Design

Total Cost €

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EC-Contrib. €

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Partnership

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Project "RESCUE" data sheet

The following table provides information about the project.

Coordinator
TALLINNA TEHNIKAULIKOOL 

Organization address
address: Ehitajate tee 5
city: TALLINN
postcode: 12616
website: www.ttu.ee

contact info
title: n.a.
name: n.a.
surname: n.a.
function: n.a.
email: n.a.
telephone: n.a.
fax: n.a.

 Coordinator Country Estonia [EE]
 Project website http://rescue-etn.eu/
 Total cost 3˙755˙824 €
 EC max contribution 3˙755˙824 € (100%)
 Programme 1. H2020-EU.1.3.1. (Fostering new skills by means of excellent initial training of researchers)
 Code Call H2020-MSCA-ITN-2016
 Funding Scheme MSCA-ITN-ETN
 Starting year 2017
 Duration (year-month-day) from 2017-04-01   to  2021-03-31

 Partnership

Take a look of project's partnership.

# participants  country  role  EC contrib. [€] 
1    TALLINNA TEHNIKAULIKOOL EE (TALLINN) coordinator 452˙529.00
2    IROC TECHNOLOGIES SA FR (GRENOBLE) participant 525˙751.00
3    POLITECNICO DI TORINO IT (TORINO) participant 516˙122.00
4    TECHNISCHE UNIVERSITEIT DELFT NL (DELFT) participant 510˙748.00
5    BRANDENBURGISCHE TECHNISCHE UNIVERSITAT COTTBUS-SENFTENBERG DE (COTTBUS) participant 498˙432.00
6    CADENCE DESIGN SYSTEMS GMBH DE (FELDKIRCHEN) participant 498˙432.00
7    IHP GMBH - INNOVATIONS FOR HIGH PERFORMANCE MICROELECTRONICS/LEIBNIZ-INSTITUT FUER INNOVATIVE MIKROELEKTRONIK DE (FRANKFURT ODER) participant 498˙432.00
8    INTRINSIC ID B.V. NL (EINDHOVEN) participant 255˙374.00

Map

 Project objective

RESCUE ITN advances scientific competences and establishes an innovative training for Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic Systems Design. Today, nanoelectronic systems are at the core of all industry sectors and deployed in life-critical application domains, such as healthcare, transportation, automotive and security, serving societal needs in Europe. They are being combined into Internet-of-Things and Cyber-Physical Systems and, ultimately, represent the physical backbone of our increasingly digitised world. Here, the impact and consequences of in-field failures, security attacks or hardware defects can be catastrophic. At the same time, they are getting very hard to avoid due to the trends of extreme complexity and miniaturisation at the doorstep of physical limits. The objective is, first, to address the demanding and mutually dependent aspects of nanoelectronic systems design, i.e. reliability, security and quality, as well as corresponding electronic design automation tools. This will rescue and enhance design of complex systems at the next generation nanoelectronics technologies. Second, it is to provide early-stage researchers with innovative training in the involved disciplines and beyond, such that they will not only be able to face today and future challenges in nanoelectronics design but also be innovative, creative, and more importantly - have an entrepreneurial mentality. The latter will help to compile ideas into products and services for EU economic and social benefits. RESCUE addresses boosting Europe’s capabilities and leadership in nanoelectronics design and creation of qualified workforce and knowledge for industry. The consortium consists of leading European research groups competent to tackle the interdependent challenges in a holistic manner and to train new top-notch interdisciplinary professionals. The ITN is excellently balanced in terms of academic and industrial training and research facilities.

 Deliverables

List of deliverables.
Comprehensive Communication Plan Documents, reports 2019-08-29 13:05:29
ESR2.3 IRP A synthetic, hierarchical abstraction approach for modelling and managing complex systems quality and reliability Documents, reports 2019-07-22 17:04:02
ESR2.4 IRP Design errors verification and debug methods for complex nanoelectronic systems Documents, reports 2019-07-22 17:03:57
ESR1.3 IRP HW/SW fault tolerance methods driven by reliability and timing constraints Documents, reports 2019-07-22 17:03:50
Report on recruitment process Documents, reports 2019-07-22 17:03:40
ESR3.2 IRP Design approaches for tamper resistant crypto implementations Documents, reports 2019-07-22 17:03:12
ESR2.1 IRP Effective techniques for secure and reliable systems validation Documents, reports 2019-07-22 17:03:58
ESR4.2 IRP EDA tools and methodologies for high quality nanoelectronic systems Documents, reports 2019-07-22 17:03:42
ESR4.3 IRP Open-source EDA tools for design quality and reliability using zamiaCAD Documents, reports 2019-07-22 17:03:13
Website, project logo and wiki-type online collaboration tool Websites, patent fillings, videos etc. 2019-07-22 17:03:23
ESR2.2 IRP Innovative real-time operating system for error management for single- and multi-core units Documents, reports 2019-07-22 17:03:52
ESR1.2 IRP Adaptive methods for fault tolerant embedded systems Documents, reports 2019-07-22 17:03:48
ESR1.5 IRP Reliable operation infrastructure for dynamic, high-dependability applications Documents, reports 2019-07-22 17:03:50
ESR1.4 IRP Techniques for detecting permanent faults during the operational phase Documents, reports 2019-07-22 17:03:51
ESR1.1 IRP Reliability analysis methods and models of memory devices Documents, reports 2019-07-22 17:03:24
ESR4.1 IRP EDA tools and methodologies for reliable nanoelectronic systems Documents, reports 2019-07-22 17:03:42
Supervisory board of the network Documents, reports 2019-07-22 17:03:50
ESR3.3 IRP Side-channel and Fault Attack resistant security primitives design Documents, reports 2019-07-22 17:03:42
ESR3.1 IRP A novel Physical Unclonable Functions technology Documents, reports 2019-07-22 17:03:08

Take a look to the deliverables list in detail:  detailed list of RESCUE deliverables.

 Publications

year authors and title journal last update
List of publications.
2019 C. C. Gürsoy, G. Medeiros, J. Chen, N. George, J. E. Rodriguez Condia, T. Lange, A. Damljanovic, A. Balakrishnan, R. Segabinazzi Ferreira, X. Lai, S. Masoumian, D. Petryk, T. Koylu, F. da Silva, A. Bagbaba, S. Hamdioui, M. Taouil, M. Krstic, P. Langendörfer, Z. Dyka, M. Huebner, J. Nolte, H. T. Vierhaus,M. Sonza Reorda, G. Squillero, L. Sterpone, J. Raik, D. Alexandrescu, M. Glorieux, G. Selimis, G. J. Schrijen, A. Klotz, C.Sauer, M. Jenihhin
RESCUE EDA Toolset for Interdependent Aspects of Reliability, Security and Quality in Nanoelectronic Systems Design
published pages: , ISSN: , DOI:
25-29 March 2019 2019-06-07
2019 Thomas Lange, Aneesh Balakrishnan, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Machine Learning to Tackle the Challenges of Transient and Soft Errors in Complex Circuits
published pages: , ISSN: , DOI:
27-28 March 2019 2019-06-07
2018 Thomas Lange, Maximilien Glorieux, Dan Alexandrescu, Luca Sterpone
Functional Failure Rate Due to Single-Event Transients in Clock Distribution Networks
published pages: , ISSN: , DOI:
20-22 June 2018 2019-06-07
2018 Thomas Lange, Maximilien Glorieux, Adrian Evans, A-Duong In, Thierry Bonnoit, Dan Alexandrescu, Cesar Boatella Polo, Carlos Urbina Ortega, Veronique Ferlet-Cavrois, Maris Tali, Ruben Garcia Alia
Single Event Characterization of a Xilinx UltraScale+ MP-SoC FPGA
published pages: , ISSN: , DOI:
4th SpacE FPGA Users Workshop - SEFUW 2018 9-11 April 2018 2019-06-07
2018 Aneesh Balakrishnan
Application of Graph Neural Network for Estimating Probabilistic Inferences in the Combinational Circuits (workshop poster with abstract)
published pages: , ISSN: , DOI:
20-22 June 2018 2019-06-07
2019 Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Moritz Fieback, Leticia Bolzani Poehls, Said Hamdioui
DFT Scheme for Hard-to-Detect Faults in FinFET SRAM
published pages: , ISSN: , DOI:
2019-06-06
2019 Josie E. Rodriguez Condia, Matteo Sonza Reorda
An extended GPGPU model to support detailed reliability analysis
published pages: , ISSN: , DOI:
SELSE-15: The 15th Workshop on Silicon Errors in Logic – System Effects 27-28 March 2019, Stanford, Cal 2019-06-06
2018 R. Cantoro, A.Damljanovic. M. Sonza Reorda and G. Squillero
Comparing different approaches to the test of Reconfigurable Scan Networks
published pages: , ISSN: , DOI:
2018 3rd International Test Sta 2019-06-06
2019 B. Du, Josie E. Rodriguez Condia, M. Sonza Reorda, L. Sterpone
IN-FIELD GPGPU TEST WITH SBST TECHNIQUES (PhD forum paper)
published pages: , ISSN: , DOI:
8th Biannual European - Latin American Summer School on Design, Test and Reliability 20-22 June, 2018, Tallinn, Esto 2019-06-06
2019 A. Damljanovic, A. Jutman, G. Squillero and A. Tsertov
Post-Silicon Validation of IEEE 1687 Reconfigurable Scan Networks
published pages: , ISSN: , DOI:
2019 IEEE European Test Symposium (ETS), Baden-Baden, Germany, 2019, to be printed 2019-06-06
2019 B. Du, Josie E. Rodriguez Condia, M. Sonza Reorda, L. Sterpone
On the evaluation of SEU effects in GPGPUs
published pages: , ISSN: , DOI:
20th IEEE Latin American Test Symposium (LATS 2019) Santiago, Chile, 11th - 13th Ma 2019-06-06
2019 R. Cantoro, A. Damljanovic, M. Sonza Reorda and G. Squillero
New techniques for reducing the duration of Reconfigurable Scan Network test
published pages: , ISSN: 1793-6454, DOI:
Journal of Circuits, Systems and Computers Vol. 28, No.1, to be printed 2019-06-06
2018 B. Du, Josie E. Rodriguez Condia, M. Sonza Reorda, L. Sterpone
IN-FIELD GPGPU TEST WITH SBST TECHNIQUES (Industrial event poster)
published pages: , ISSN: , DOI:
NVIDIA GPU Tecnology Conference (GTC Europe 2018) 23-25 October, 2018, Munich, Ge 2019-06-06
2018 G.C. Medeiros, L.M. Bolzani Poehls, M. Taouil, F. Luis Vargas, S. Hamdioui
A defect-oriented test approach using on-Chip current sensors for resistive defects in FinFET SRAMs
published pages: 355-359, ISSN: 0026-2714, DOI: 10.1016/j.microrel.2018.07.092
Microelectronics Reliability 88-90 2019-05-28
2018 D. Petryk, Z. Dyka, P. Langendörfer
Fault Injections: Most Often Used Setups
published pages: , ISSN: , DOI:
2019-05-28
2018 Thomas Lange, Maximilien Glorieux, Adrian Evans, A-Duong In, Dan Alexandrescu, Cesar Boatella-Polo, Carlos Urbina Ortega, Véronique Ferlet-Cavrois, Maris Tali, Rubén Garcı́a Alı́a
Single Event Characterization of a Xilinx UltraScale+ MP-SoC FPGA
published pages: , ISSN: , DOI:
2019-05-28
2018 D. Petryk, Z. Dyka, P. Langendörfer
Optical Fault Injections: a Setup Comparison
published pages: , ISSN: , DOI:
2019-05-28
2018 Maximilien Glorieux, Adrian Evans, Thomas Lange, A-Duong In, Dan Alexandrescu, Cesar Boatella-Polo, Rubén Garcı́a Alı́a, Maris Tali, Carlos Urbina Ortega, Maria Kastriotou, Pablo Fernández-Martı́nez, and Véronique Ferlet-Cavrois
Single-Event Characterization of Xilinx UltraScale+ r MPSOC under Standard and Ultra-High Energy Heavy-Ion Irradiation
published pages: , ISSN: , DOI:
2019-05-28
2018 B. Du, Josie E. Rodriguez Condia, M. Sonza Reorda, L. Sterpone
In-Field GPGPU Test with SBST Techniques
published pages: , ISSN: , DOI:
2019-05-28
2018 J.-C. Chen, M. Krstic
Engineering of Cross-Layer Fault Tolerance In Multiprocessing Systems
published pages: , ISSN: , DOI:
2019-05-28
2018 Josie E. Rodriguez Condia, B. Du, M. Sonza Reorda, L. Sterpone
On the functional test of the GPGPU scheduler
published pages: , ISSN: , DOI:
2019-05-28
2018 F. Augusto da Silva, A. C. Bagbaba, S. Hamdioui and C. Sauer
Use of Formal Methods for verification and optimization of Fault Lists in the scope of ISO26262
published pages: , ISSN: , DOI:
2019-05-28
2018 A. C. Bagbaba, F. Augusto da Silva, C. Sauer
Improving the Confidence Level in Functional Safety Simulation Tools for ISO 26262
published pages: , ISSN: , DOI:
2019-05-28

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