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ULKCOND SIGNED

Zero damage Ultra-Low-K etch using the precursor CONDensation technique

Total Cost €

0

EC-Contrib. €

0

Partnership

0

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 ULKCOND project word cloud

Explore the words cloud of the ULKCOND project. It provides you a very rough idea of what is the project "ULKCOND" about.

optimizing    named    intrinsic    damaging    damage    damascene    reactions    plasma    dielectric    porosity    semiconductor    conductor    5nm    etching       silicate    transistor    accordingly    resistivity    nm    zero       phenomenon    50    explored    manufacturing    improvement    cmos    skills    metal    deg    deposited    al    micro    causing    scaling    decrease    nanotechnology    cu    consequence    amongst    delay    signal    materials    applies    law    temperature    successful    electronics    cryogenic    away    sio2    size    domains    stops    permittivity    lower    since    bulk    moore    industry    technique    dielectrics    first    electronic    glasses    capacitance    replaced    pore    extend    polishing    circuit    compatible    organo    node    structure    economic    beginning    evolution    60    deposition    porous    ultimately    transmission    insulating    removal    career    etched    profile    lowered    capillary    locally    besides    interconnects    rc    condensation    followed    delayed    never    patterned    nowadays    excess   

Project "ULKCOND" data sheet

The following table provides information about the project.

Coordinator
INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM 

Organization address
address: KAPELDREEF 75
city: LEUVEN
postcode: 3001
website: www.imec.be

contact info
title: n.a.
name: n.a.
surname: n.a.
function: n.a.
email: n.a.
telephone: n.a.
fax: n.a.

 Coordinator Country Belgium [BE]
 Total cost 160˙800 €
 EC max contribution 160˙800 € (100%)
 Programme 1. H2020-EU.1.3.2. (Nurturing excellence by means of cross-border and cross-sector mobility)
 Code Call H2020-MSCA-IF-2015
 Funding Scheme MSCA-IF-EF-ST
 Starting year 2016
 Duration (year-month-day) from 2016-04-01   to  2018-03-31

 Partnership

Take a look of project's partnership.

# participants  country  role  EC contrib. [€] 
1    INTERUNIVERSITAIR MICRO-ELECTRONICA CENTRUM BE (LEUVEN) coordinator 160˙800.00

Map

 Project objective

Since the beginning of the electronic evolution, size of transistor never stops to decrease accordingly to Moore’s law. This scaling applies also to the interconnects, composed by conductor and insulating materials, leading to an overall increase of the resistivity of the conductor and the dielectric’s capacitance, ultimately causing delayed signal transmission (so-called RC delay). In order to decrease the resistivity, Al was replaced by Cu as a conductor. The circuit’s capacitance can be lowered by using materials with lower dielectric permittivity, named low-k’s. Nowadays, the most successful low-k dielectrics are porous organo-silicate glasses, with porosity up to 50%, pore size around 1.5-2 nm and k-values down to 1.8 (k=4.2 for bulk SiO2). Interconnects are nowadays built by the Damascene technique, where the dielectric is first deposited, then locally etched away, followed by metal deposition in the patterned structure and polishing for metal excess removal. Due to their intrinsic porosity, most of processing steps cause low-k damage, amongst which plasma etching is the most damaging. The present proposal aims at understanding and optimizing zero-damage cryogenic etching of low-k materials, compatible with the micro-electronics industry (at temperature above -60°C). Besides the improvement of the etching process and the better understanding of reactions damaging the low-k materials during plasma etching, this work will investigate the phenomenon of micro-capillary condensation into porous materials, which is not widely explored and can lead to other applications in micro-electronics and in other nanotechnology domains. This research project will contribute to enable the so-called 5nm node in future CMOS manufacturing, and as a consequence it will have a wide economic impact. Finally, this research will allow the applicant to extend his technical and project management skills, strengthening his profile for a future career in the semiconductor industry or R&D.

 Publications

year authors and title journal last update
List of publications.
2016 F.Leroy, N. Brochu, R. Chanson, R.Dussart, T. Tillocher, J.‑F. de Marneffe, L Zhang, K. Maekawa, K. Yatsuda, S. Tahara, C. Dussarrat
Comparison of C4F8 and Higher boiling point organic for low-k cryo-etching
published pages: , ISSN: , DOI:
2019-06-13
2017 R. Chanson, J.F. de Marneffe, K. Babaei Gavan, F. Lazzarino, T. Yamaguchi, K. Yatsuda
Option for low damage processing during FSAV : GPPS and alternative plug
published pages: , ISSN: , DOI:
2019-06-13
2017 R. CHANSON, S. Tahara, K. Sasa, C. Dussarrat, R. Dussart, T. Tillocher, P. Lefaucheux, J-F de marneffe
Low-k cryo-etching : Comparison of four different High Boiling Point Organic (HBPO)
published pages: , ISSN: , DOI:
2019-06-13
2017 R. Chanson, N. Holtzer, P. Lefaucheux, R. Dussart, P. Shen, K. Urabe, C. Dussarat, K. Maekawa, K. Yatsuda, S. Tahara and J.-F. de Marneffe
Low damage ULK etching by means of high boiling point organic condensation
published pages: , ISSN: , DOI:
2019-06-13
2016 R. Chanson, J-F. De Marneffe, R. Dussart, T. Thomas, L. Philippe
Cryo-etching for low-k integration : Phenomenon screening from condensation to damages propagation a 0 damage process is reached
published pages: , ISSN: , DOI:
2019-06-13
2017 Romain Chanson, Philippe Lefaucheux, Remi Dussart, Tillocher Thomas, Peng Shen, Keiichiro Urabe, Christian Dussarat, Kaoru Maekawa, Koichi Yatsuda, Shigeru Tahara, Jean-Francois de Marneffe
Cryo-etching for integration in micro-electronic : Silicon deep etch for contact and low-k integration in Back end of line (BEOL)
published pages: , ISSN: , DOI:
2019-06-13
2017 R. CHANSON, S. Tahara, K. Sasa, C. Dussarat, R. Dussart, T. Thillocher, P. Lefaucheux, J-F demarneff
Cryo-etching: fundamental mechanisms
published pages: , ISSN: , DOI:
2019-06-13

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