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European Exascale System Interconnect and Storage

Total Cost €


EC-Contrib. €






 ExaNeSt project word cloud

Explore the words cloud of the ExaNeSt project. It provides you a very rough idea of what is the project "ExaNeSt" about.

commercial    platform    throughput    turning    validate    direction    communication    first    phases    memories    hyper    chain    applicability    complete    follow    minimum    soon    integration    located    overheads    reducing    commercialization    resilient    density    experts    skills    energy    solution    etp4hpc    maintenance    ownership    subsequent    packaging    sourced    spectrum    ip    brings    scheme    roadmap    property    maintaining    databases    structures    storage    hpc    modular    building    resilience    200    big    mitigation    connectivity    complexity    interconnect    deployment    industrial    frameworks    racks    reliability    sw    data    decade    steered    algorithms    locality    suitable    kernel    rack    physical    congestion    entire    unified    exascale    environmental    validated    distributed    models    simulate    simulations    volatile    model    guarantees    cooling    compute    latency    efficiency    architectural    business    intelligence    architecture    prototype    computing    qos    exanest   

Project "ExaNeSt" data sheet

The following table provides information about the project.


Organization address
address: N PLASTIRA STR 100
postcode: 70013

contact info
title: n.a.
name: n.a.
surname: n.a.
function: n.a.
email: n.a.
telephone: n.a.
fax: n.a.

 Coordinator Country Greece [EL]
 Project website
 Total cost 8˙442˙547 €
 EC max contribution 8˙442˙547 € (100%)
 Programme 1. H2020-EU.1.2.2. (FET Proactive)
 Code Call H2020-FETHPC-2014
 Funding Scheme RIA
 Starting year 2015
 Duration (year-month-day) from 2015-12-01   to  2019-05-31


Take a look of project's partnership.

# participants  country  role  EC contrib. [€] 
5    MONETDB SOLUTIONS BV NL (AMSTERDAM) participant 651˙000.00
7    ENGINSOFT SPA IT (TRENTO) participant 520˙625.00
8    VIRTUAL OPEN SYSTEMS FR (GRENOBLE) participant 450˙000.00
11    EXACT LAB SRL IT (TRIESTE) participant 220˙000.00
12    ARM LIMITED UK (CAMBRIDGE) participant 85˙798.00
13    ALLINEA SOFTWARE LIMITED UK (WARWICK) participant 84˙201.00


 Project objective

ExaNeSt will develop, evaluate, and prototype the physical platform and architectural solution for a unified Communication and Storage Interconnect and the physical rack and environmental structures required to deliver European Exascale Systems. The consortium brings technology, skills, and knowledge across the entire value chain from computing IP to packaging and system deployment; and from operating systems, storage, and communication to HPC with big data management, algorithms, applications, and frameworks. Building on a decade of advanced R&D, ExaNeSt will deliver the solution that can support exascale deployment in the follow-up industrial commercialization phases. Using direction from the ETP4HPC roadmap and soon-available high density and efficiency compute, we will model, simulate, and validate through prototype, a system with: 1. High throughput, low latency connectivity, suitable for exascale-level compute, their storage, and I/O, with congestion mitigation, QoS guarantees, and resilience. 2. Support for distributed storage located with the compute elements providing low latency that non-volatile memories require, while reducing energy, complexity, and costs. 3. Support for task-to-data sw locality models to ensure minimum data communication energy overheads and property maintenance in databases. 4. Hyper-density system integration scheme that will develop a modular, commercial, European-sourced advanced cooling system for exascale in ~200 racks while maintaining reliability and cost of ownership. 5. The platform management scheme for big-data I/O to this resilient, unified distributed storage compute architecture. 6. Demonstrate the applicability of the platform for the complete spectrum of Big Data applications, e.g. from HPC simulations to Business Intelligence support. All aspects will be steered and validated with the first-hand experience of HPC applications and experts, through kernel turning and subsequent data management and application analysis.


List of deliverables.
Implementation notes for the storage and data access infrastructure Other 2020-02-07 12:58:11
Requirement analysis (network and storage) and Porting Roadmap Documents, reports 2020-02-07 12:58:11
Preliminary Dissemination report Documents, reports 2020-02-07 12:58:11
Census of the applications Documents, reports 2020-02-07 12:58:11

Take a look to the deliverables list in detail:  detailed list of ExaNeSt deliverables.


year authors and title journal last update
List of publications.
2019 José Duro, Jose A. Pascual, Salvador Petit, Julio Sahuquillo, María E. Gómez
Modeling and analysis of the performance of exascale photonic networks
published pages: e4773, ISSN: 1532-0626, DOI: 10.1002/cpe.4773
Concurrency and Computation: Practice and Experience 2020-02-07
2018 Manolis Katevenis, Roberto Ammendola, Andrea Biagioni, Paolo Cretaro, Ottorino Frezza, Francesca Lo Cicero, Alessandro Lonardo, Michele Martinelli, Pier Stanislao Paolucci, Elena Pastorelli, Francesco Simula, Piero Vicini, Giuliano Taffoni, Jose A. Pascual, Javier Navaridas, Mikel Luján, John Goodacre, Bernd Lietzow, Angelos Mouzakitis, Nikolaos Chrysos, Manolis Marazakis, Paolo Gorlani, Stefano
Next generation of Exascale-class systems: ExaNeSt project and the status of its interconnect and storage development
published pages: 58-71, ISSN: 0141-9331, DOI: 10.1016/j.micpro.2018.05.009
Microprocessors and Microsystems 61 2020-02-07
2018 R. Ammendola, A. Biagioni, F. Capuani, P. Cretaro, G. De Bonis, F. Lo Cicero, A. Lonardo, M. Martinelli, P. Paolucci, E. Pastorelli, L. Pontisso, F. Simula, P. Vicini
The brain on low power architectures: Efficient simulation of cortical slow waves and asynchronous states
published pages: 760-769, ISSN: , DOI: 10.3233/978-1-61499-843-3-760
Advances in Parallel Computing Vol. 32 2020-02-07
2018 Sebastian Werner, Javier Navaridas, Mikel Luján
A Survey on Optical Network-on-Chip Architectures
published pages: 1-37, ISSN: 0360-0300, DOI: 10.1145/3131346
ACM Computing Surveys 50/6 2020-02-07
2018 R. Ammendola, A. Biagioni, F. Capuani, P. Cretaro, G. De Bonis, F. Lo Cicero, A. Lonardo, M. Martinelli, P. Paolucci, E. Pastorelli, L. Pontissio, F. Simula and P. Vicini
Large scale low power computing system: status of network design in ExaNeSt and EuroEXA projects
published pages: , ISSN: , DOI: 10.3233/978-1-61499-843-3-750
Advances in Parallel Computing 2020-02-07
2017 R. Ammendola, A. Biagioni, P. Cretaro, O. Frezza, F. Lo Cicero, A. Lonardo, M. Martinelli, P. S. Paolucci, E. Pastorelli, F. Simula, P. Vicini, G. Taffoni, John Goodacree, Mikel Lujn, J. Navaridas, J. P. Saiz, N. Chrysos, and M. Katevenis for the ExaNeSt team
The next Generation of Exascale-class Systems: the ExaNeSt Project
published pages: , ISSN: , DOI: 10.5281/zenodo.823595
Euromicro Conference on Digital System Design (DSD 2017) 2020-02-07
2017 Jose Duro, Salvador Petit, Julio Sahuquillo and Maria E. Gomez
Modeling a Photonic Network for Exascale Computing
published pages: , ISSN: , DOI: 10.5281/zenodo.823624
3rd International Workshop on Modeling and Simulation of Parallel and Distributed Systems (MSPDS 2017) 2020-02-07
2019 J. Lant, J. Navaridas, A. Attwood, M. Lujan and J. Goodacre
Enabling Standalone FPGA Computing
published pages: , ISSN: , DOI:
IEEE Symposium on High Performance Interconnects 2020-02-07
2019 Navaridas, J., Lant, J., Pascual Saiz, J., Luján, M., & Goodacre, A.
Design Exploration of Multi-tier interconnection networks s for Exascale systems
published pages: TBD, ISSN: , DOI:
ICPP 2019 : International Conference on Parallel Processing 2020-02-07
2018 Jose A. Pascual, Joshua Lant, Caroline Concatto, Andrew Attwood, Javier Navaridas, Mikel Luján, John Goodacre
On the effects of allocation strategies for exascale computing systems with distributed storage and unified interconnects
published pages: e4784, ISSN: 1532-0626, DOI: 10.1002/cpe.4784
Concurrency and Computation: Practice and Experience 2020-02-07
2017 Angelos Mouzakitis, Christian Pinto, Nikolay Nikolaev, Alvise Rigo, Daniel Raho, Babis Aronis, Manolis Marazakis
Lightweight and Generic RDMA Engine Para-virtualization for the KVM Hypervisor
published pages: , ISSN: , DOI: 10.5281/zenodo.807607
2017 International Conference on High Performance Computing & Simulation (HPCS 2017) 2020-02-07
2017 Sebastian Werner, Javier Navaridas, Mikel Luján
Efficient Sharing of Optical Resources in Low-Power Optical Networks-on-Chip
published pages: 364, ISSN: 1943-0620, DOI: 10.1364/jocn.9.000364
Journal of Optical Communications and Networking 9/5 2020-02-07
2017 Alejandro Erickson, Iain A. Stewart, Javier Navaridas, Abbas E. Kiasari
The stellar transformation: From interconnection networks to datacenter networks
published pages: 29-45, ISSN: 1389-1286, DOI: 10.1016/j.comnet.2016.12.001
Computer Networks 113 2020-02-07
2019 Javier Navaridas, Jose A. Pascual, Alejandro Erickson, Iain A. Stewart, Mikel Luján
INRFlow: An interconnection networks research flow-level simulation framework
published pages: 140-152, ISSN: 0743-7315, DOI: 10.1016/j.jpdc.2019.03.013
Journal of Parallel and Distributed Computing 130 2020-02-07
2018 Joshua Lant, Caroline Concatto, Andrew Attwood, Jose A. Pascual, Mike Ashworth, Javier Navaridas, Mikel Luján, John Goodacre
Enabling shared memory communication in networks of MPSoCs
published pages: e4774, ISSN: 1532-0626, DOI: 10.1002/cpe.4774
Concurrency and Computation: Practice and Experience 2020-02-07
2018 D. Goz, S. Bertocco, L. Tornatore, G. Taffoni
Direct N-Body code designed for heterogeneous platforms
published pages: , ISSN: , DOI: 10.20371/inaf/pub/2018_00002
INAF 2020-02-07
2018 D. Goz, L. Tornatore, S. Bertocco & G. Taffoni
Performance of direct N-body code on ARM64 SoC
published pages: , ISSN: , DOI: 10.20371/inaf/pub/2018_00006
INAF-OATS Technical Report 2020-02-07
2019 M. Ploumidis, N.D. Kallimanis, M. Asiminakis, N. Chryos, P. Xirouchakis, M. Gianoudis, L. Tzanakis, N. Dimou, A. Psistakis, P. Peristerkis, G. Kalokairinos, V. Papaefstathiou and M. Katevenis
Software and Hardware co-design for low power HPC Platforms
published pages: , ISSN: , DOI:
Exacomm 2020-02-07
2017 R Ammendola, A Biagioni, P Cretaro, O Frezza, F Lo Cicero, A Lonardo, M Martinelli, P S Paolucci, E Pastorelli, F Pisani, F Simula, P Vicini, J Navaridas, F Chaix, N Chrysos, M Katevenis, V Papaeustathiou
Low latency network and distributed storage for next generation HPC systems: the ExaNeSt project
published pages: 82045, ISSN: 1742-6588, DOI: 10.1088/1742-6596/898/8/082045
Journal of Physics: Conference Series 898 2020-02-07
2018 Sergio Lechago, Carlos García-Meca, Nuria Sánchez-Losilla, Amadeu Griol, Javier Martí
High signal-to-noise ratio ultra-compact lab-on-a-chip microflow cytometer enabled by silicon optical antennas
published pages: 25645, ISSN: 1094-4087, DOI: 10.1364/oe.26.025645
Optics Express 26/20 2020-02-07
2017 Alejandro Erickson, Iain A. Stewart, Jose A. Pascual, Javier Navaridas
Improved routing algorithms in the dual-port datacenter networks HCN and BCN
published pages: 58-71, ISSN: 0167-739X, DOI: 10.1016/j.future.2017.05.004
Future Generation Computer Systems 75 2020-02-07
2017 Alejandro Erickson, Abbas E. Kiasari, Javier Navaridas, Iain A. Stewart
An Optimal Single-Path Routing Algorithm in the Datacenter Network DPillar
published pages: 689-703, ISSN: 1045-9219, DOI: 10.1109/TPDS.2016.2591011
IEEE Transactions on Parallel and Distributed Systems 28/3 2020-02-07
2017 Anastasios Papagiannis, Giorgos Saloustros, Manolis Marazakis, Angelos Bilas
published pages: 3-11, ISSN: 0163-5980, DOI: 10.1145/3041710.3041713
ACM SIGOPS Operating Systems Review 50/1 2020-02-07
2019 Joshua Lant, Javier Navaridas, Andrew Attwood, Mikel Lujan and John Goodacre
Enabling Standalone FPGA Computing
published pages: , ISSN: , DOI:
IEEE Micro 2020-02-07
2018 D. Goz, L. Tornatore, S. Bertocco & G. Taffoni
Direct N-body code designed for cluster based on heterogeneous computational nodes
published pages: , ISSN: , DOI: 10.20371/inaf/pub/2018_00005
INAF-OATS Technical Report 2020-02-07
2017 Carlos García-Meca, Sergio Lechago, Antoine Brimont, Amadeu Griol, Sara Mas, Luis Sánchez, Laurent Bellieres, Nuria S Losilla, Javier Martí
On-chip wireless silicon photonics: from reconfigurable interconnects to lab-on-chip devices
published pages: e17053-e17053, ISSN: 2047-7538, DOI: 10.1038/lsa.2017.53
Light: Science & Applications 6/9 2020-02-07
2019 M. Kynigos, J. Navaridas and J.A. Pascual
Scalability of a Silicon Photonic Switch for High Performance Interconnects
published pages: , ISSN: , DOI:
Emit 2020-02-07
2019 J. Lant, J. Navaridas
Direct Communications between Disributed FPGA
published pages: , ISSN: , DOI:
Emit 2020-02-07
2018 Kyriakos Paraskevas, Nikolaos Chrysos, Vassilis Papaefstathiou, Pantelis Xirouchakis, Panagiotis Peristerakis, Michalis Giannioudis, Manolis Katevenis
Virtualized Multi-Channel RDMAwith Software-Defined Scheduling
published pages: 82-90, ISSN: 1877-0509, DOI: 10.1016/j.procs.2018.08.240
Procedia Computer Science 136 2020-02-07
2016 Jose Puche, Sergio Lechago, Salvador Petit, María E. Gómez and Julio Sahuquillo
Accurately Modeling a Photonic NoC in a Detailed CMP Simulation Framework
published pages: , ISSN: , DOI: 10.5281/zenodo.804004
Workshop on Modeling and Simulation of Parallel and Distributed Systems 2020-02-07
2016 Ying Zhang, Dimitar Nedev, Panagiotis Koutsourakis, and Martin Kersten
Distributed Processing and Transaction Replication in MonetDB - Towards a Scalable Analytical Database System in the Cloud
published pages: , ISSN: , DOI: 10.5281/zenodo.803988
Final Public Workshop from LeanBigData and CoherentPaaS 2020-02-07

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